Mity CPU Platforms » MitySOM-5CSX Altera Cyclone V

07/18/2017

JK 07:56 PM Software Development: RE: I2C Slave Communication Hanging

Some additional context / correction:
I2C2 and I2C3 are both configured the same way. If you replace "3" with "2" in the above example, and replace "DVI" with "TFT" (related to our ST1633 touch controller), the result is the I2C2 setu... Jared Kirschner

CS 07:33 PM Software Development: RE: I2C Slave Communication Hanging

All,
This is the open drain primitive we are using for the I2C interfaces:
wire w_i2c3_scl_oe, w_i2c3_scl, w_i2c3_sda_oe, w_i2c3_sda;
assign DVI_SCL = (w_i2c3_scl_oe) ? 1'b0 : 1'bz;
assign DVI_SDA = (w_i2c3_sda_oe) ? 1'b0 : 1'b... Clyde Shappee

MW 05:09 PM Software Development: RE: I2C Slave Communication Hanging

Are you using the open drain primitive in the top level of the FPGA project?
-Mike
Michael Williamson

JK 05:00 PM Software Development: RE: I2C Slave Communication Hanging

I've attached the driver source/header. I'm waiting to hear from the touch controller vendor whether I can share the protocol description. Jared Kirschner

JK 04:50 PM Software Development: RE: I2C Slave Communication Hanging

We are using I2C2 routed through the FPGA fabric (see image "I2C2_Connector.PNG"). It does have pullups to the best of my knowledge (see image "I2C2_Pullups.PNG").
Though we initially tried to communicate via user space, the vendor in... Jared Kirschner

MW 04:32 PM Software Development: RE: I2C Slave Communication Hanging

Also, Can you share a snippet of the user space code you are using to issue the read request?
Thanks.
-Mike
Michael Williamson

MW 04:15 PM Software Development: RE: I2C Slave Communication Hanging

Which I2C bus are you using? An HPS peripheral connected directly to HPS pins or routed via FPGA fabric?
This almost looks like there is no pull-up on the bus...
-Mike
Michael Williamson

JK 02:52 PM Software Development: I2C Slave Communication Hanging

We're experiencing a problem with I2C communications with a slave on address 0x55 on a MitySOM-5CSX, shown in the attached image (scope_3.png).
In the image, *a read is attempted, with the first byte NACK'd by the slave, and an invali... Jared Kirschner

07/13/2017

HB 03:29 PM FPGA Development: RE: I2C Controller

Thank you, this was resolved, turned out to be a problem with our build scripts. Harrison Barclay

07/12/2017

TI 12:06 PM FPGA Development: RE: I2C Controller

Harrison
Whenever you change anything to do with HPS pin assignments, you will need to rebuild the preloader and update it on the boot media (SD card or ROM)
https://support.criticallink.com/redmine/projects/mityarm-5cs/wiki/Building... Tim Iskander

07/11/2017

HB 05:51 PM FPGA Development: I2C Controller

Hello,
Unsure whether to post this under the software or FPGA topic.
We are transitioning from a mostly working system developed on the Mitysom5CSX Devkit to a custom carrier board design (Cyclone V, 5CSX-H6-4YA-RC). In the previou... Harrison Barclay

07/04/2017

TI 03:13 PM Software Development: RE: Accessing NOR flash from Linux on 5CSX

We have a wiki page relating to using the quad spi NOR [primarily centered around booting from NOR]
(https://support.criticallink.com/redmine/projects/mityarm-5cs/wiki/Utilizing_QSPI_NOR_Memory).
The bulk of it is standard linux mtd s... Tim Iskander

BK 08:10 AM Software Development: RE: Accessing NOR flash from Linux on 5CSX

Thanks Tim, that's good news.
Is there any specific doc. for the 5CSZ build? e.g. driver name, build instructions, code location, etc. Any examples kicking about? Do you know if anybody has tried this on the 5CSX?
Kind regards... Bruce Kenny

07/03/2017

TI 05:22 PM Software Development: RE: Accessing NOR flash from Linux on 5CSX

Bruce
Linux has excellent support for NOR flash devices using the mtd subsytem
http://www.linux-mtd.infradead.org/
You can read/write the device (or partition on the device) as a block or install a filesystem (such as jffs or ubifs) o... Tim Iskander

BK 04:53 PM Software Development: Accessing NOR flash from Linux on 5CSX

Our project is currently in the design phase and we are considering using a small amount of NOR flash to read and write some information.
The question is whether there are built in Linux drivers to do this?
We only have a small amo... Bruce Kenny

06/20/2017

AB 05:59 PM FPGA Development: RE: Power fail interrup

Clyde,
Offhand our recommendation would be to utilize an HPS GPIO and have it configured in the GPIO controller as an interrupt.
Additionally it would be pertinent to know how long you expect power to persist after this interrupt ... Alexander Block

CS 05:14 PM FPGA Development: RE: Power fail interrupt

What more is there to say, really? We have a low voltage supervisor in our design and when the power is going to fail, we would like to take the necessary precautions before power is completely gone. Clyde Shappee

DV 04:45 PM FPGA Development: RE: Power fail interrup

Hello Clyde,
Could you describe the situation a bit more?
Thanks!
Dan Daniel Vincelette

CS 02:05 PM FPGA Development: Power fail interrup

What is the recommended input to the SOM for a power fail interrupt?
clyde Clyde Shappee