Activity
From 05/22/2017 to 06/20/2017
06/20/2017
- AB 05:59 PM FPGA Development: RE: Power fail interrup
- Clyde,
Offhand our recommendation would be to utilize an HPS GPIO and have it configured in the GPIO controller as an interrupt.
Additionally it would be pertinent to know how long you expect power to persist after this interrupt ... - CS 05:14 PM FPGA Development: RE: Power fail interrupt
- What more is there to say, really? We have a low voltage supervisor in our design and when the power is going to fail, we would like to take the necessary precautions before power is completely gone.
- DV 04:45 PM FPGA Development: RE: Power fail interrup
- Hello Clyde,
Could you describe the situation a bit more?
Thanks!
Dan - What is the recommended input to the SOM for a power fail interrupt?
clyde
06/14/2017
- Hello, I have a 5CSX-H6-4YA-RI board.
What do I pull the MSEL lines up to when I pull them up.
(what is VCCPGM pins set to ?)
Can I set VCCBAT to +3.3V ?
06/07/2017
- JK 02:20 PM Software Development: RE: Using EEPROM available on MitySOM-5CSX
- Hello Mike and Adam,
I very much appreciate you both providing other suggestions readily available with our MitySOM.
We don't have a lot of data that we need to store off the SD card (well under 1 kB). Most of it will probably be w...
06/02/2017
- MW 12:14 PM Software Development: RE: Using EEPROM available on MitySOM-5CSX
- The QSPI NOR is supported by the MTD layer, so you should be able to partition it and mount it using JFFS2 (or perhaps UBIFS, but I personally don't have a lot of experience with that) or even access it RAW if you like with flash_eraseal...
- SS 12:05 PM Software Development: RE: Using EEPROM available on MitySOM-5CSX
- We're using the 5CSX-H6-4YA so we should have 32MB of QSPI NOR, and we are booting from SD card, though it's possible we may want to put the preloader + uboot in their so we can TFTP a new SD image.
If we did use the QSPI NOR, what ... - AD 10:25 AM Software Development: RE: Using EEPROM available on MitySOM-5CSX
- Hi Jared,
If you are looking for a small amount of space, there is also some memory available in the RTC. There is 256B of battery backed RAM on the AB1805-T3 RTC. Assuming you have a battery, this will hold the data until the batte...
06/01/2017
- MW 11:52 PM Software Development: RE: Using EEPROM available on MitySOM-5CSX
- Hi Jared,
Before you get into the I2C EEPROM, does the MitySOM you are using have the QSPI NOR FLASH installed (most do)? If you are booting from SD card than that should be wide open (and ranges from 8 to 32 MB depending on the inst... - +Context:+
My team would like to store some non-volatile data specific to a unit of hardware (independent of the SD card / image) in our system, and decided the appropriate place to store this information would be the EEPROM available...
05/23/2017
- DV 08:32 PM Software Development: RE: Altera spi
- Brian,
Glad to hear it! You're welcome
Dan - BW 06:24 PM Software Development: RE: Altera spi
- Dan,
Got it working. Thanks for all the help.
Brian - DV 06:12 PM Software Development: RE: Altera spi
- Brian,
It looks like the Altera GPIO documentation is wrong, in the the driver it's looking for GPIO interrupts to be set with "altr,interrupt-type", not the documented "altr,interrupt-trigger". In the 3.16 kernel it was "altr,interru... - BW 05:57 PM Software Development: RE: Altera spi
- Dan,
I just tried this and I'm getting the same error. I posted my updated dts.
Thanks,
Brian - BW 05:55 PM Software Development: RE: Altera spi
- Dan,
I just tried this and I'm getting the same error. I posted my updated dts.
Thanks,
Brian - DV 05:28 PM Software Development: RE: Altera spi
- Brian,
I think this variable was changed to "altr,interrupt-trigger" in the newer kernel. Here is the documentation for the device-tree bindings of the Altera GPIO core: https://github.com/altera-opensource/linux-socfpga/blob/socfpga-... - BW 05:23 PM Software Development: RE: Altera spi
- Dan,
I have most of it working. The only problem I see now is the gpio not showing up. I'm getting the following errors:
altera_gpio ff200160.gpio: altr,interrupt-type value not set in device tree
/soc/bus@0ff200000/gpio@0160: regist... - DV 02:38 PM Software Development: RE: Altera spi
- Brian,
Can you post your boot output?
I would recommend doing a diff of the DE0 nano board dts and that one. There could be some new additions or changes because of the differences in kernel versions.
- DV 08:21 PM Software Development: RE: Virtual SPI device setup and access using spidev - Altera Cyclone V case
- Glad to hear you got it to work!
Dan - GC 06:48 PM Software Development: RE: Virtual SPI device setup and access using spidev - Altera Cyclone V case
- Dan,
solved also this step!
I rebuilt the my kernel version using the default .config you suggested me, modified to enable other feature I need to use, and here it is!
I've also managed to use a custom version of spidev.c, that I n... - DV 05:20 PM Software Development: RE: Virtual SPI device setup and access using spidev - Altera Cyclone V case
- Glad to hear!
I used our mitysom5csx_devkit_defconfig that is part of our 3.16 kernel
kernel: https://support.criticallink.com/gitweb/?p=linux-socfpga.git;a=summary
defconfig: https://support.criticallink.com/gitweb/?p=linux-socfp... - GC 05:04 PM Software Development: RE: Virtual SPI device setup and access using spidev - Altera Cyclone V case
- Dan,
thanks for it.
I've added the spi0 section at the bottom of my dts and it works!!! Fantastic!!
The only point is that is works only using your uImage, not with mine... that's now my next issue.
But in any case I'm moving on ... - DV 02:32 PM Software Development: RE: Virtual SPI device setup and access using spidev - Altera Cyclone V case
- Hello Gianni,
I see that you've tried to add both the spidev devices to a FPGA spi core and the HPS peripheral. I would recommend going with the HPS peripheral because there is a known bug with the FPGA spi core and spidev, as discuss...
05/22/2017
- BW 07:59 PM Software Development: RE: Altera spi
- Dan,
I compiled the rel_socfpga-4.1.33-ltsi-rt_17.05.01_pr branch of the kernel form altera open source. I replaced the config file with the mitysom5csx_devkit_defconfig. I am having trouble with the DTS. When using the dts you provided...