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From 01/27/2017 to 02/25/2017

02/22/2017

MR 10:27 PM PCB Development: Standoff on Mounting Hole Locations page
I believe there is a small errata on the [[Mounting_Hole_Locations]] page.
At the bottom it states... "Standoff: McMaster Carr PN - 91115A510" ... This is not an actual part number in McMaster.
I think the last two numbers where switch...
Michael Ruen

02/08/2017

SS 10:16 AM PCB Development: Thermal Management, Datasheet Table 6, Commercial or Industrial
Hello,
Regarding Table 6 in the datasheet, is this information valid for the commercial or industrial temperature range modules?
Thanks a lot,
Steve
Stephen Snyder

02/02/2017

AD 12:57 PM FPGA Development: RE: CLK2DDR signal on development board
Hello Franco,
Thanks for checking before committing to the board... The I/O standard does indeed sound like a mismatch!
The likely difference between the 2.5V I/O design building and a failing 3.3V I/O design is due to the (VPD) P...
Adam Dziedzic
FS 11:47 AM FPGA Development: CLK2DDR signal on development board
Hi, I'm designing my own carrier card, but I've some doubts about the use of the bank 4A.
I need to connect the the mitysom module some parallel DACs with 3.3 volts single ended levels as outputs.
I need about 34 pins so I was planning...
franco spinella
 

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