Activity
From 01/16/2017 to 02/14/2017
02/08/2017
- Hello,
Regarding Table 6 in the datasheet, is this information valid for the commercial or industrial temperature range modules?
Thanks a lot,
Steve
02/02/2017
- AD 12:57 PM FPGA Development: RE: CLK2DDR signal on development board
- Hello Franco,
Thanks for checking before committing to the board... The I/O standard does indeed sound like a mismatch!
The likely difference between the 2.5V I/O design building and a failing 3.3V I/O design is due to the (VPD) P... - Hi, I'm designing my own carrier card, but I've some doubts about the use of the bank 4A.
I need to connect the the mitysom module some parallel DACs with 3.3 volts single ended levels as outputs.
I need about 34 pins so I was planning...
01/16/2017
- AB 05:17 PM Software Development: RE: 5CSX-H6-42A Dev.Kit does not boot from SD
- Ben,
Thank you for providing the device specific details.
I wanted to let you know that on Friday 1/13/2017 I sent you an e-mail requesting additional company specific information, that I wasn't sure you would want to post on the f...