Mity CPU Platforms » MitySOM-5CSX Altera Cyclone V

10/05/2016

DV 08:09 PM Software Development: RE: Increase POSIX message queue size

Hello,
One quick question, are the ! before the * meant to be there?
I will try to reproduce this issue tomorrow, I'll report back once I do.
Dan Daniel Vincelette

DV 08:04 PM Software Development: RE: Using PREEMPT_RT on MitySOM 5CSX Dev Board

You are also correct in using the uBootMMCEnv.txt from our git repo. The other one is a much older version, which should actually do the same thing but the one from the git repo is the latest and greatest. Daniel Vincelette

DV 08:00 PM Software Development: RE: Using PREEMPT_RT on MitySOM 5CSX Dev Board

Jared,
I was able to reproduce your problem and I've found the issue. Between our 3.16 kernel and the 4.1.22 kernel it looks like some of the device tree attributes for the altera pio core were changed. Also the updated device tree do... Daniel Vincelette

DV 05:38 PM Software Development: RE: Using PREEMPT_RT on MitySOM 5CSX Dev Board

Hi Jared,
From what you've seen it looks to me to be an issue with the 4.1.22 kernel. I've looked at qsys/dts and they look fine. Tonight I will build the 4.1.22 RT kernel and try that on our dev kit (using everything from our dev kit... Daniel Vincelette

JK 05:31 PM Software Development: RE: Using PREEMPT_RT on MitySOM 5CSX Dev Board

Additional information:
I've stepped through the u-boot process manually (after parsing the differences between the two uBootMMCEnv.txt files mentioned above) to make sure the FPGA is actually being programmed and verified that it con... Jared Kirschner

TI 02:58 PM Software Development: RE: Accessing git repositories when behind firewall

Sorry, it was not clear that the https access is _new_ :)
Not sure about the gethostbyname failure... support.criticallink.com is the valid hostname.
Thanks for the tidbit on SSL no verify...
We are looking in to the cert path i... Tim Iskander

MK 10:29 AM Software Development: RE: Accessing git repositories when behind firewall

> The URL for each repository is formed from @https://support.criticallink.com/git/<repos.git>@
It was my 1st guess, that corresponding https urls exist, but it was not evident to find them ...
> ...
That leads to error:
@
gethostb... Mladen Kerep

TI 08:20 AM Software Development: RE: Accessing git repositories when behind firewall

https access has been enabled for Critical Link repositories on https://support.criticallink.com
The URL for each repository is formed from @https://support.criticallink.com/git/<repos.git>@
If you try to access git via the https pro... Tim Iskander

10/04/2016

MK 09:08 AM Software Development: Increase POSIX message queue size

I've rebuild the linux kernel acc. "Building the Linux Kernel Wiki":https://support.criticallink.com/redmine/projects/mityarm-5cs/wiki/Linux_Kernel and enabled the POSIX Message queues by setting the kernel config parameter @CONFIG_POSIX... Mladen Kerep

MK 08:35 AM Software Development: Accessing git repositories when behind firewall

The instructions on the wiki use the "git protocol":https://git-scm.com/book/tr/v2/Git-on-the-Server-The-Protocols for accessing the repositories. I'm trying to clone from within the company but cloning fails with error " _support.critic... Mladen Kerep

10/03/2016

JK 02:54 PM Software Development: RE: Using PREEMPT_RT on MitySOM 5CSX Dev Board

Hi Dan,
Our hardware engineer just noted a significant difference between two versions of uBootMMCEnv.txt listed on Critical Link's website regarding the MitySOM 5CSX.
One is in the git repository for the development board, and it'... Jared Kirschner

JK 12:16 PM Software Development: RE: Using PREEMPT_RT on MitySOM 5CSX Dev Board

Hi Dan,
Requested files attached; let me know if I'm missing anything (e.g., FPGA source code).
Also, not sure if this is related to the problem... whenever I have one PIO in the DTS, it shows up as /sys/class/gpio/gpiochip480. Tha... Jared Kirschner

DV 12:04 PM Software Development: RE: Using PREEMPT_RT on MitySOM 5CSX Dev Board

Hi Jared,
Would you mind posting your .qsys file and .dts?
I'll take a quick sanity check,
Thanks
Dan Daniel Vincelette

09/30/2016

JK 12:02 PM Software Development: RE: Using PREEMPT_RT on MitySOM 5CSX Dev Board

Addendum: any single PIO (0 through 3) can be enabled in the DTS and the system will boot, but including more than one causes the boot process to hang. Jared Kirschner

JK 08:13 AM Software Development: RE: Using PREEMPT_RT on MitySOM 5CSX Dev Board

Hi Dan,
I did a bit more experimenting with including a subset of the hps_lw_bus sub-nodes. I confirmed with the Verilog developer on our team that the FPGA image file I'm using has the PIO cores and System ID core present in the stoc... Jared Kirschner

09/29/2016

MR 09:13 AM Software Development: RE: Ethernet not coming up

I tested the crystal with an oscilloscope and found the crystal had gone bad. After replacing the crystal everything is working again. Thanks all for the help. Michael Ruen

DV 12:07 AM Software Development: RE: Ethernet not coming up

Hi Michael,
Sorry for the delayed response.
Would you mind running ethtool and posting the result? Daniel Vincelette

DV 12:21 AM Software Development: RE: SPI on MitySOM

Hi Brian,
The following device tree uses the SPIM perpherials: http://support.criticallink.com/gitweb/?p=linux-socfpga.git;a=blob;f=arch/arm/boot/dts/socfpga_mitysom5csx_leigh.dts;h=867961f12818e92b1dd6872fb5b05f11bbc60dea;hb=73a206bd... Daniel Vincelette

09/28/2016

DV 11:59 PM Software Development: RE: Using PREEMPT_RT on MitySOM 5CSX Dev Board

Hi Jared,
The hps_lw_bus node and all sub nodes are for any FPGA related logic that is attached to the HPS Light weight bridge. For the dev kit there are 3 PIO cores and a System ID core attached to this bus. If the FPGA image that is... Daniel Vincelette

BW 04:10 PM Software Development: RE: SPI on MitySOM

dts attached Brian Wentworth

BW 04:06 PM Software Development: SPI on MitySOM

Hi,
I am trying to communicate using the SPIM0 on the HPS with 5CSE-H4-3YA. SPIM0 HPS I/O Set 0 is selected in the QSYS project and the correct multiplexing seems to be in effect for the use of SPIM0.CLK, SPIM0.MOSI, SPIM0.MISO, SPIM0... Brian Wentworth

09/26/2016

JK 09:26 AM Software Development: RE: Using PREEMPT_RT on MitySOM 5CSX Dev Board

Hello Dan,
I'm now working to create a custom DTS, using socfpga_cyclone5_sockit.dts as a starting point, which incorporates elements of the MitySOM 5CSX DTS. When using the 4.1.22 LTSI RT kernel with socfpga_defconfig and socfpga_cyc... Jared Kirschner

09/22/2016

MR 09:07 AM Software Development: RE: Ethernet not coming up

Yup, tried it with 3 cables (patch, patch and crossover) and 3 devices (switch, router and laptop).
The switch it's usually plugged into is 10/100. Michael Ruen

09/21/2016

MW 08:25 PM Software Development: RE: Ethernet not coming up

Just out of curiosity, have you tried a different cable? Do you have a switch or anything available to try?
Most PC's have 1Gb ethernet links, and I note your connection message indicated 100 Mbps. Wondering if you have a bad cabl... Michael Williamson

MR 06:00 PM Software Development: RE: Ethernet not coming up

Well it's doing it again. No ethernet. Tried running the gpio test, didn't do anything. When I plug an ethernet cable in, the link light on the dev board's ethernet will give a really quick flash, also windows will recognize the connecti... Michael Ruen

AD 04:27 PM Software Development: RE: Ethernet not coming up

I'm not sure why it would fail like that, then recover without any real changes. The HPS_GPIO28 controls the Ethernet PHY Reset. If this was set low, the PHY would be held in reset. That being said, the boot log shows that this GPIO s... Adam Dziedzic

MR 12:56 PM Software Development: RE: Ethernet not coming up

I may have fixed it. On the prebuilt image there is the program gpiotest. I ran it just for the heck of it, and here's what I got...
root@mitysom-5csx:~# ./gpiotest
Usage: gpioprog PinFile
root@mitysom-5csx:~# stmmaceth ff702000.ether... Michael Ruen

MR 12:22 PM Software Development: Ethernet not coming up

I turned the board on today with my custom SD image (FPGA, kernel, file structure...) that I have been using the past couple weeks, only to find the ethernet did not enable. I thought it must have been something with my image, so I loade... Michael Ruen

09/08/2016

SS 08:06 AM FPGA Development: RE: HDMI Output splash screen is intermittently displayed on boot

Hi Dan,
Thanks for posting the instructions and looking at the higher resolution operation. This is very useful as it's possible we'll want to support a resolution that needs greater than 4MB for a framebuffer. We'll be using these ... Stephen Snyder

09/07/2016

DV 06:21 PM FPGA Development: RE: HDMI Output splash screen is intermittently displayed on boot

Alright, so I was able to get 1080p working. I had to make some changes to the defconfig for the hdmi example. I had to add support for CONFIG_CMA and CONFIG_DMA_CMA, which allowed the altera vip frame buffer driver to allocate enough co... Daniel Vincelette

DV 10:58 AM FPGA Development: RE: HDMI Output splash screen is intermittently displayed on boot

That's a good idea Mike, it looks like the kernel defaults vram to 4MB but for this framebuffer 8MB+ is required. I'll try setting it higher and see if I can get 1080p working today.
Thanks,
Dan Daniel Vincelette

09/06/2016

MW 08:21 PM FPGA Development: RE: HDMI Output splash screen is intermittently displayed on boot

Can you up the video ram buffer available for allocation using the kernel parameter of the format below? Michael Williamson

DV 06:29 PM FPGA Development: RE: HDMI Output splash screen is intermittently displayed on boot

Alright my testing today wasn't as successful as I'd liked. I tried both 1920x1080 and 720x576. Doing 1920x1080 caused the kernel to crash when it tried to allocate the RAM for the frame buffer to use. 720x576 appeared to boot fine but m... Daniel Vincelette

DV 09:38 AM FPGA Development: RE: HDMI Output splash screen is intermittently displayed on boot

Hi Steve,
I'm testing this now. Hopefully it's just the mods to the device tree/qsys project. I'll update once my build is finished and (fingers crossed) I'm able to get video.
Dan Daniel Vincelette