Mity CPU Platforms » MitySOM-5CSX Altera Cyclone V

12/11/2014

AB 07:50 PM FPGA Development: 100MHz Input clock (CLK2 - DDR3) Issue

A customer has the 100MHz DDR3 clock being fed into the module through Pins 117 and 119 on a custom carrier board and is using it to clock some ADC data. However after a little run-time it stops working as noted below: Alexander Block

11/25/2014

MW 07:46 AM FPGA Development: RE: Writing to HPS memory

I would recommend contacting your Arrow FAE or Altera for help with the device tree generation / sopcinfo file.
You will need to create a new preloader and uboot and device tree block. You may also need to rebuild the kernel with the... Michael Williamson

VG 07:39 AM FPGA Development: Writing to HPS memory

Hi,
I'm want to use the hps_ddr_write_example design from critical link and test it on Arrow Terasic Cyclone V SOCKit .
I have changed the device and the HPS DDR3 parameters in the Quartus project.Also I'm using the Arrow kit's DDR3 ... Vidya Govindan