Mity CPU Platforms » MitySOM-5CSX Altera Cyclone V

11/07/2014

DV 02:22 PM FPGA Development: RE: Modular SGDMA

Hi Jack,
We don't have any explicit examples of this but you will want to look into the userspace I/O driver. This should allow you to map in the FPGA interrrupts to a /dev/uio device.
I did a bit of searching and this looks like a... Daniel Vincelette

11/05/2014

01:40 PM FPGA Development: RE: Modular SGDMA

Hi Dan,
The issue seems to be with the polling. I brought out the empty signal to an oscilloscope and found that it is on, but for some reason I'm not reading that on the software side.
I think it's better to switch to interrupt to... Anonymous

10/29/2014

CK 10:58 AM Software Development: RE: Performance problem with baremetal code

In the meanwhile and after an ARM Cortex training I've found the root cause of the problem:
For enabling the caches, you have also to initialize the MMU, e.g. with the attached version of performance.c. Nevertheless the baremetal code... Christian Kempter

10/20/2014

04:34 PM FPGA Development: RE: Modular SGDMA

Hi Dan,
I polling the FIFO empty signal for the both the dispatcher and write master to ensure that only when both FIFOs are empty when I will continue.
The delay varies, it's hard to predict.
Ideally we don't want to put any sl... Anonymous

10/17/2014

DV 04:53 PM FPGA Development: RE: Modular SGDMA

Hi Jack,
You could try polling the dispatcher's busy bit instead but I'm not quite sure if that would solve your issue. Any idea at how long the delay is for? Does the FIFO overflow because of it? Also you might want to put a bit of a... Daniel Vincelette

03:57 PM FPGA Development: Modular SGDMA

Hi
I'm running into a difficulty with the Modular SGDMA that is used in the HPS Memory example.
I have to send dispatchers repeatedly in a infinite loop. I have it designed such that after I send the command to write the dispatcher... Anonymous