Activity
From 07/21/2014 to 08/19/2014
08/15/2014
- AB 01:44 PM Software Development: RE: How to add aditional HPS GPIO's
- In the case described of wanting to add GPIO's to drive/control an LED (output from the HPS) you do not need to alter the DTS file. The DTS additions were for Switch based GPIO's which are a special case in which their is a Linux driver ...
08/14/2014
- Posting on behalf of a customer:
On the MitySom .dts file, you specify some GPIOS like this: - AB 10:49 AM Software Development: RE: PCI-e Device Driver - munmap related error
- Reporting that the customer solved their problem:
I've solved the problem.
Thread A which was signaling Thread B to terminate was doing a pthread_join after doing so.
I commented out the pthread_join and it worked perfectly fine...
08/13/2014
- PB 04:21 PM Software Development: RE: Standard USB peripheral connection on MitySOM eval Board
- Hi Mike,
Happy to hear that a procedure is needed because I tried many things to make it work (I noticed that in the 09/13 delivered image, my USB key was powered on, but not accessible).
I'll wait for your instructions.
Kind rega...
08/11/2014
- MW 07:23 AM Software Development: RE: Miscellaneous questions
- Note:
you need to add "meta-openembedded/meta-oe" as the layer, not just "meta-openembedded".
-Mike
- MW 07:21 AM Software Development: RE: Miscellaneous questions
- Hi,
Sorry. The i2c-tools recipe is part of the meta-openembedded layer that you don't get by default from the basic yocto process.
You need to download that layer (git clone) and add it to your build/conf/bblayers.conf file. - PB 07:14 AM Software Development: RE: Miscellaneous questions
- Hi Mike,
adding "i2c-tools" to IMAGE_INSTALL_append gives me this error while executing "bitbake core-image-basic" :
ERROR: Nothing RPROVIDES 'i2c-tools' (but /home/user/yocto/poky/meta/recipes-extended/images/core-image-basic.bb RDE...
08/04/2014
- MW 10:06 AM Software Development: RE: Standard USB peripheral connection on MitySOM eval Board
- Hello Mr. Bretecher,
We will try to get a procedure posted for this. Sorry for the delay.
-Mike
- MW 10:05 AM Software Development: RE: Miscellaneous questions
- Memtool and the i2c-utils aren't added to our reference filesystem image, but you could add it by modifying the IMAGE_INSTALL_append variable in your local.conf file to include "i2c-tools" as well as "memtool".
We will push an update ... - MW 09:51 AM Software Development: RE: Performance problem with baremetal code
- Hello Mr. Kempter,
We don't normally run / support bare-metal applications here (we find most folks get into more trouble using bare-metal with this class of processor).
It looks like the linux application is running at the correct...
08/01/2014
- I tried to do some performance analysis of ARM on MitySOM-5CSX regarding floating point performance in baremetal code. Therefore I wrote the two modules performance.c and mul.c.
*performace.c:*
07/25/2014
- MW 02:42 PM Software Development: RE: PCI-e Device Driver - munmap related error
- Can you post your code? Are you getting user space faults and not kernel oops, right?
Are you unmapping with the same size as with your mmap() call?
-Mike
- Posting on behalf of a customer:
I'm having some sporadic problems with the device driver I made for our pci-e device.
It works great in general but it seems like every other run, I get a segfault when trying to
close() the device...
07/24/2014
- AD 09:05 AM FPGA Development: RE: FPGA DDR3 on 5CSX-H6-42A-RC-X (DDR)
- Hi Nigel,
I don't believe there is a way to do it directly in QSYS. You may be able to patch your generated outputs to get over that hurdle. As you would expect, Altera has the normal minimum frequency requirement programmed in so u... - ND 07:59 AM FPGA Development: RE: FPGA DDR3 on 5CSX-H6-42A-RC-X (DDR)
- Hi Adam,
Thanks for the insights.
Do you know how to persuade qsys to run the DDR at a slower speed? In normal use it will not allow anything less than 300MHz.
Thanks,
Nigel.
07/23/2014
- AD 04:19 PM FPGA Development: RE: FPGA DDR3 on 5CSX-H6-42A-RC-X (DDR)
- Hi Nigel,
You are correct, the C8ES devices do not meet timing with the FPGA DDR according to Quartus. The ES silicon was not qualified to any faster speed grades than C8, though it does work according to our tests. We designed the ... - Although your reference design using FPGA DDR compiles as supplied, when I select the correct device (5CSXFC6C6U23C8ES) for my hardware I get timing violations on the FPGA DDR that I have been unable to fix.
I cannot create extra marg...
07/21/2014
- Hi,
I'm using the pre-dev MitySOM eval board and I'm trying to rebuild a complete working environment with the current yocto poky distro (linux 3.12) as instructed in the wiki.
Most stuff is working but I have some open question :...