Activity
From 07/04/2014 to 08/02/2014
08/01/2014
- I tried to do some performance analysis of ARM on MitySOM-5CSX regarding floating point performance in baremetal code. Therefore I wrote the two modules performance.c and mul.c.
*performace.c:*
07/25/2014
- MW 02:42 PM Software Development: RE: PCI-e Device Driver - munmap related error
- Can you post your code? Are you getting user space faults and not kernel oops, right?
Are you unmapping with the same size as with your mmap() call?
-Mike
- Posting on behalf of a customer:
I'm having some sporadic problems with the device driver I made for our pci-e device.
It works great in general but it seems like every other run, I get a segfault when trying to
close() the device...
07/24/2014
- AD 09:05 AM FPGA Development: RE: FPGA DDR3 on 5CSX-H6-42A-RC-X (DDR)
- Hi Nigel,
I don't believe there is a way to do it directly in QSYS. You may be able to patch your generated outputs to get over that hurdle. As you would expect, Altera has the normal minimum frequency requirement programmed in so u... - ND 07:59 AM FPGA Development: RE: FPGA DDR3 on 5CSX-H6-42A-RC-X (DDR)
- Hi Adam,
Thanks for the insights.
Do you know how to persuade qsys to run the DDR at a slower speed? In normal use it will not allow anything less than 300MHz.
Thanks,
Nigel.
07/23/2014
- AD 04:19 PM FPGA Development: RE: FPGA DDR3 on 5CSX-H6-42A-RC-X (DDR)
- Hi Nigel,
You are correct, the C8ES devices do not meet timing with the FPGA DDR according to Quartus. The ES silicon was not qualified to any faster speed grades than C8, though it does work according to our tests. We designed the ... - Although your reference design using FPGA DDR compiles as supplied, when I select the correct device (5CSXFC6C6U23C8ES) for my hardware I get timing violations on the FPGA DDR that I have been unable to fix.
I cannot create extra marg...
07/21/2014
- Hi,
I'm using the pre-dev MitySOM eval board and I'm trying to rebuild a complete working environment with the current yocto poky distro (linux 3.12) as instructed in the wiki.
Most stuff is working but I have some open question :...
07/20/2014
- Hi,
I originally wanted to connect to the board either usb storage peripherals or webcams-like peripherals. I bought a MiniUSB-B to Standard-A receptacle adapter. When I try to connect a simple USB stick, it is neither recognized nor...
07/17/2014
- DV 05:08 PM Software Development: RE: Pre production (-X) modules with newer sd image
- That update to the conf/local.conf should fix the uImage issue. As for the building of the DTB through yocto, we pushed a patch to our git server about a week ago that should of addressed that issue, patch: http://support.criticallink.co...
- PB 03:42 PM Software Development: RE: Pre production (-X) modules with newer sd image
- Thanks a lot for the feedback.
I have noticed that the Yocto wiki has just been updated concerning the uimage format.
For the rootfs tarball, I intended to do what you proposed but I wasn't selfconfindent. Your post helps me !
Kind ... - ND 09:13 AM Software Development: RE: Pre production (-X) modules with newer sd image
- I am currently working through the kit and having a similar experience. The following seems to work for me in regard to your yocto question.
Add the files from the modules image to the core image - same directory (lib/modules/3.12.0-x...
07/15/2014
- PB 06:28 PM Software Development: RE: Pre production (-X) modules with newer sd image
- Well, the orange LED switches OFF because with this new version of the SD card, the FPGA is loaded with a firmware at u-boot time. OK
I still have open questions, among them :
- I'm unable to recreate the dtb file I can find on the...
07/11/2014
- ND 09:34 AM Software Development: RE: Building u-Boot and Preloader
- I believe that the files in question need to be copied from software/spl_bsp/generated into u-boot-socfpga/board/cl/mitysom-5csx, is that correct and is there anything else that needs to be copied?
Thanks,
Nigel.
07/10/2014
- ND 02:23 PM Software Development: RE: Breaking changes on early MityARM
- Should have spotted that note but somehow managed to miss it!
Thanks,
Nigel. - MW 02:00 PM Software Development: RE: Breaking changes on early MityARM
- Hello Nigel,
Sorry about that. The description of the hardware changes for the Dev Kit baseboard are here:
https://support.criticallink.com/redmine/projects/5csxbase/wiki/Errata_and_Product_Change_Notifications
The only signifi... - I have an early MityARM module and dev kit. On trying to implement the latest software versions I found that the Ethernet interface was not functional. On investigating it appears that there has been a pcb change on the RGMIII_RESETn sig...
- I am just revisiting the development kit after working on other projects and I am trying to locate the copy_files.sh script that is referenced on the building u-Boot wiki page.
It is not in the tools/scripts folder, or anywhere else t...
07/08/2014
- Hi,
I'am just starting to discover the eval kit. The one I ordered from Mouser was a pre-prod (- X) version. I understand from the errata sheet that the identified issues are not a problem for me (FPGA DDR, QSPI Nor, RVB LED).
I have...
07/07/2014
- Hi,
Do you have sample c/c++ program to read/write a memory inside Cyclone V FPGA through hps2fpga bridge interface?
Thanks.