Activity

From 06/10/2014 to 07/09/2014

PB 12:17 PM Software Development: Pre production (-X) modules with newer sd image: Hi,
I'am just starting to discover the eval kit. The one I ordered from Mouser was a pre-prod (- X) version. I understand from the errata sheet that the identified issues are not a problem for me (FPGA DDR, QSPI Nor, RVB LED).
I have... Pierre-Yves BRETECHER

BL 07:22 AM Software Development: Sample c program to read/write Cyclone V FPGA internal memory through hps2fpga bridge: Hi,
Do you have sample c/c++ program to read/write a memory inside Cyclone V FPGA through hps2fpga bridge interface?
Thanks. Bill Lee

AD 05:14 PM FPGA Development: RE: How to access FPGA internal memory through AXI slave interface protocol: Hi Bill,
Sorry for the confusion. The latest image updated the Baud Rate to 115.2kbps to be consistent with the rest of the Critical Link modules.
- Adam Adam Dziedzic
BL 05:05 PM FPGA Development: RE: How to access FPGA internal memory through AXI slave interface protocol: Hi,
I downloaded the sd_image_mitysom_5csx_rev1B.zip, and extracted out the .bin file. Then I typed "sudo dd if=sd_image_mitysom_5csx_rev1B.bin of=/dev/sdb bs=1M" into a brand new 8GB MicroSDHC sd card. Next, I typed "sync" as instruc... Bill Lee

AB 09:27 PM FPGA Development: RE: How to access FPGA internal memory through AXI slave interface protocol: Information on how to make an SD card based upon the current Development Kit SD card image (Rev 1B) can be found on this wiki page (https://support.criticallink.com/redmine/projects/mityarm-5cs/wiki/Building_SD_Card_Image) in the "Develo... Alexander Block
BL 06:17 PM FPGA Development: RE: How to access FPGA internal memory through AXI slave interface protocol: Mike,
I think you meant "memtool -32 0xFFD0501C=0x06" for brgmodrst register. The reset value of the register somehow shows "0x00000000". So, I set it to 0x7, then 0x6, to make sure the hps2fpga bridge get reset and release the reset.... Bill Lee
MW 08:52 AM FPGA Development: RE: How to access FPGA internal memory through AXI slave interface protocol: For reference on the reset register:
http://www.altera.com/literature/hb/cyclone-v/hps.html#reg_default_component/register_rstmgr_brgmodrst.html
Michael Williamson
MW 08:51 AM FPGA Development: RE: How to access FPGA internal memory through AXI slave interface protocol: Hi Bill,
It looks like you are using version 3.8 of the kernel. Version 3.8 does not have the FPGA bridge drivers that provide the sysfs layers.
I believe we are now shipping DevKits that use a 3.12 version of the kernel as the ba... Michael Williamson

BL 09:52 PM FPGA Development: RE: How to access FPGA internal memory through AXI slave interface protocol: Hi Mike,
I attached 2 files as you indicated in your previous reply. One is boot.log and another one is foo.txt.
Let me describe my intention and building flow to you.
1. I have a function need to be implemented in FPGA with HPS b... Bill Lee
MW 07:56 AM FPGA Development: RE: How to access FPGA internal memory through AXI slave interface protocol: If you can't see the enable file then the driver for the device isn't compiled in or the device tree blob doesn't instantiate it. You typically don't want to enable the bridge until the FPGA is loaded.
Can you attach your full boot l... Michael Williamson

BL 10:46 PM FPGA Development: RE: How to access FPGA internal memory through AXI slave interface protocol: Thanks for your reply.
I am currently intend to use hps2fpga bridge only in my design. And I just copy the generated rbf file into SD card and loaded it into FPGA by using "cat file.rbf > /dev/fpga0". By refering to the 2nd link from ... Bill Lee
MW 08:12 AM FPGA Development: RE: How to access FPGA internal memory through AXI slave interface protocol: Which AXI crossbar interface are you using? The hps2fpga bridge or the lightweight bridge? Did you make a new preloader?
Ref: http://www.altera.com/literature/hb/cyclone-v/cv_54005.pdf
You must ensure that you are enabling the br... Michael Williamson
01:00 PM Software Development: UART RS232: Hi,
Could you point to some examples for UART RS232 communication?
Thanks,
Jack Anonymous

BL 10:43 PM FPGA Development: How to access FPGA internal memory through AXI slave interface protocol: Hi,
I have implemented a logic and loaded into cyclone V FPGA. Before that, I did run simulation to access a memory, which was generated by Megafunctions Wizard and is inside of FPGA. After I loaded the image of my design, I need to f... Bill Lee

MW 08:45 AM Software Development: RE: Using custom DTS in yocto flow: Right now, the kernel recipe that gets used for our dev kit is indeed in the meta-mitysom-5csx/recipes-kernel/linux folder.
You will need to get familiar with "bitbake":http://www.yoctoproject.org/docs/1.6/bitbake-user-manual/bitbak... Michael Williamson

DV 05:23 PM Software Development: Using custom DTS in yocto flow: Posting on behalf of a customer and for future reference as well:
How do you get yocto to use a custom dts instead of the socfpga_mitysom5csx_devkit.dts?
The customer will be checking the kernel source and dts into version control ... Daniel Vincelette

MW 11:04 AM Software Development: RE: I2C Access with 5CSX Development Board: 1) i2cset and i2cget are pretty standard tools, do you need help installing them or do you not want them on your final OS? We can provide an RPM package for them if you are using the standard filesystem provided with the DevKit.
2) t... Michael Williamson

AB 12:42 PM Software Development: I2C Access with 5CSX Development Board: Posting on behalf of a customer and for future reference as well:
1) How do I access the +5V I2C current monitor IC interface on the Critical Link development board, WITHOUT using i2cSet and i2cGet? I do not have these programs instal... Alexander Block

07:55 PM Software Development: RE: Reading memory into a file: Actually don't worry about it.
We managed to solve it.
Thanks,
Jack Anonymous

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Mity CPU Platforms » MitySOM-5CSX Altera Cyclone V