Mity CPU Platforms » MitySOM-5CSX Altera Cyclone V

03/26/2014

05:33 PM Software Development: RE: Interrupt & Device Tree

I tried to generate the device tree file from the sopcinfo file produced by quartus.
I used the following command
$ sopc2dts --input mityarm_5csx_dev_board.sopcinfo --output socfpga.dts
And I got a statement like this
Master and ... Anonymous

05:20 PM Software Development: Interrupt & Device Tree

Hi,
Do you guys have any example on how to handle a interrupt? I have it set up in Qsys, where I have a FIFO sending its interrupt signal to the HPS. But how do I handle it on the software side.
I read that I need device tree to se... Anonymous

03/21/2014

RB 06:15 PM FPGA Development: RE: Time limited SOF file question

Hi Mike,
Never mind my last post, I found the jtag breakout board in my original shipment.
-rb
Rich Bagdazian

RB 06:09 PM FPGA Development: RE: Time limited SOF file question

Thanks Mike,
Makes sense. I have a Terasic USB Blaster as shown in the attached PDF file.
What's the best way to interface the USB blaster to the white breakout connector on the MityArm Board?
Rich
Rich Bagdazian

MW 03:19 PM FPGA Development: RE: Time limited SOF file question

Hi Rich,
This is an answer from our Altera FAE:
_You can’t create .rbf files from time limited sof files. The concern is that you could put the .rbf in flash and reconfigure every hour to avoid paying for the IP. Some our 3rd pa... Michael Williamson

RB 02:04 PM FPGA Development: Time limited SOF file question

I built a component into the FPGA that includes an instance of the Altera FIR II compiler.
At the end of the build, the final output is named: mityarm_5csx_dev_board_time_limited.sof
The file converter utility does not seem to be wil... Rich Bagdazian

03/20/2014

12:36 PM Software Development: RE: Reading memory into a file

Hi,
Is there a way for memtool to output the memory into a file?
Thanks,
Jack Anonymous