Activity
From 02/16/2014 to 03/17/2014
03/05/2014
- GG 05:24 PM Software Development: RE: Reading memory into a file
- Hi Jack,
It may take us some time to get to the bottom of this. We'll post in this thread as soon as we have additional information.
Please keep us informed if you run into any issues with the current work around of not running '... -
12:51 PM
Software Development: RE: Reading memory into a file
- Any update on this??
03/03/2014
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05:59 PM
Software Development: RE: Reading memory into a file
- Hi Greg,
I have no problem with the software wihtout first sending the command to enable the SDRAM. The data that I get from memtool matches the data that I get from my software.
Thanks!
Jack - GG 05:56 PM Software Development: RE: Reading memory into a file
- Hi Jack,
Do you run into any problems if you use your software without first sending the command to enable the SDRAM? We'll try to get you an explanation for what you're seeing and in the mean time try using your software without run... -
03:45 PM
Software Development: RE: Reading memory into a file
- Hi,
I managed to read memory into a file but we got another problem.
We are following your example - write to hps memory. In that example a command has to be issued in order to write to memory via the FPGA
memtool -32 0xffc25080...
02/27/2014
- BD 02:40 PM Software Development: RE: Reading memory into a file
- Jack,
We don't have any general examples to provide.
If you're trying to share data over FTP or ssh in a human-readable format, you can use fprintf to print the data from memory into a file.
http://www.cplusplus.com/reference/... - Hi,
Do you have any examples on reading memory in software?
We need to grab the data we have in memory into a file and export it via Ethernet.
Thanks!
Jack
02/22/2014
- MW 07:48 AM Software Development: RE: Yocto Plug-In Python.exe Error
- Can you post a capture of your complete shell interaction?
02/20/2014
- DV 02:39 PM FPGA Development: RE: HPS Memory Controller
- Nope, if you connect it to the HPS to FPGA bridge you can treat it more like a register that the code on the HPS reads. You could also use the FPGA to HPS bridge to write to a specific location in memory, though I have no experience with...
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01:10 PM
FPGA Development: RE: HPS Memory Controller
- Hi Dan,
Don't you mean connect it to the FPGA to HPS AXI bridge?
Our input data is processed in the FPGA.
Thanks!
Jack - DV 01:03 PM FPGA Development: RE: HPS Memory Controller
- At that rate it might be simpler to create a FIFO in the FPGA and connect it to the light weight HPS to FPGA bridge. Then have the HPS poll that register continuously. We've run that interface at 100Mhz, mainly for control and status reg...
02/19/2014
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05:33 PM
FPGA Development: RE: HPS Memory Controller
- Also, I'm trying to by pass the SGDMA dispatcher and use the write master directly.
Jack -
05:32 PM
FPGA Development: RE: HPS Memory Controller
- Hi Dan,
Our data is coming in at about 40 MHz,
Jack - DV 04:57 PM FPGA Development: RE: HPS Memory Controller
- Hi Jack,
Looking in the SGDMA dispatcher core user guide, it appears that if you use the extended descriptors you can set the write stride to zero, which would allow you to continuous write to the same address.
What is your require... -
04:33 PM
FPGA Development: RE: HPS Memory Controller
- Hi Dan,
Regarding the SGDMA Write Master Core. I looked through the document for this core and it doesn't give any information on these questions.
For the write command sink port, what exactly is the purpose of "write stride" (91-7... - DV 03:40 PM FPGA Development: RE: HPS Memory Controller
- Jack,
We do not currently have an example that uses a non-packetized Avalon stream. There should be an option in the SGDMA controller to disable packets but we haven't tried to use it.
Dan -
03:22 PM
FPGA Development: RE: HPS Memory Controller
- Hi,
Do you have any write to HPS memory examples where I can send data into the memory in a continuous stream rather than a packet at a time?
Thanks!
Jack