Mity CPU Platforms » MitySOM-5CSX Altera Cyclone V

02/27/2014

BD 02:40 PM Software Development: RE: Reading memory into a file

Jack,
We don't have any general examples to provide.
If you're trying to share data over FTP or ssh in a human-readable format, you can use fprintf to print the data from memory into a file.
http://www.cplusplus.com/reference/... Bob Duke

02:21 PM Software Development: Reading memory into a file

Hi,
Do you have any examples on reading memory in software?
We need to grab the data we have in memory into a file and export it via Ethernet.
Thanks!
Jack Anonymous

02/22/2014

MW 07:48 AM Software Development: RE: Yocto Plug-In Python.exe Error

Can you post a capture of your complete shell interaction? Michael Williamson

02/20/2014

DV 02:39 PM FPGA Development: RE: HPS Memory Controller

Nope, if you connect it to the HPS to FPGA bridge you can treat it more like a register that the code on the HPS reads. You could also use the FPGA to HPS bridge to write to a specific location in memory, though I have no experience with... Daniel Vincelette

01:10 PM FPGA Development: RE: HPS Memory Controller

Hi Dan,
Don't you mean connect it to the FPGA to HPS AXI bridge?
Our input data is processed in the FPGA.
Thanks!
Jack Anonymous

DV 01:03 PM FPGA Development: RE: HPS Memory Controller

At that rate it might be simpler to create a FIFO in the FPGA and connect it to the light weight HPS to FPGA bridge. Then have the HPS poll that register continuously. We've run that interface at 100Mhz, mainly for control and status reg... Daniel Vincelette

02/19/2014

05:33 PM FPGA Development: RE: HPS Memory Controller

Also, I'm trying to by pass the SGDMA dispatcher and use the write master directly.
Jack Anonymous

05:32 PM FPGA Development: RE: HPS Memory Controller

Hi Dan,
Our data is coming in at about 40 MHz,
Jack Anonymous

DV 04:57 PM FPGA Development: RE: HPS Memory Controller

Hi Jack,
Looking in the SGDMA dispatcher core user guide, it appears that if you use the extended descriptors you can set the write stride to zero, which would allow you to continuous write to the same address.
What is your require... Daniel Vincelette

04:33 PM FPGA Development: RE: HPS Memory Controller

Hi Dan,
Regarding the SGDMA Write Master Core. I looked through the document for this core and it doesn't give any information on these questions.
For the write command sink port, what exactly is the purpose of "write stride" (91-7... Anonymous

DV 03:40 PM FPGA Development: RE: HPS Memory Controller

Jack,
We do not currently have an example that uses a non-packetized Avalon stream. There should be an option in the SGDMA controller to disable packets but we haven't tried to use it.
Dan Daniel Vincelette

03:22 PM FPGA Development: RE: HPS Memory Controller

Hi,
Do you have any write to HPS memory examples where I can send data into the memory in a continuous stream rather than a packet at a time?
Thanks!
Jack Anonymous

02/13/2014

DV 03:02 PM FPGA Development: RE: Signal Tap & JTAG FPGA Programming

Glad to hear you got it working.
Dan Daniel Vincelette

03:01 PM FPGA Development: RE: Signal Tap & JTAG FPGA Programming

Hi Dan,
Yes it works with the rbf file and it works when I program it in Linux. No problems there.
I managed to get it programming with the JTAG.
Thanks again for your help!
Jack
Anonymous

DV 01:58 PM FPGA Development: RE: Signal Tap & JTAG FPGA Programming

Hi Jack,
I've just created a wiki page for the steps that it takes to program the FPGA using the USB-Blaster, would you mind trying that and telling me where it fails and at what percent of the progress bar it fails at?
The link is... Daniel Vincelette

12:58 PM FPGA Development: Signal Tap & JTAG FPGA Programming

Hi,
I'm raised the issue before regarding programming the FPGA with JTAG.
I have tried programming via JTAG, the driver is installed and Quartus does recognize it, but it always fails when I attempt to program it.
I need to use ... Anonymous

02/07/2014

JL 11:29 AM Software Development: Bitbake Error

I am running into the current error while running bitbake:
jliriano@ArmDev:~/yocto/build$ bitbake u-boot
ERROR: Execution of event handler 'external_linaro_toolchain_version_handler' failed
Traceback (most recent call last):
Fil... Julio Liriano

02/03/2014

AB 03:55 PM Software Development: Yocto Plug-In Python.exe Error

Posting on behalf of a customer: Alexander Block

01/30/2014

GG 10:01 AM FPGA Development: RE: Ethernet

Edited my response. Good eye Dave. Thanks! Gregory Gluszek

DR 09:31 AM FPGA Development: RE: Ethernet

Greg,
Only 2 "e"s in setenv, not three... Jack probably knows that, but just to be clear...
Dave
David Rice

GG 09:10 AM FPGA Development: RE: Ethernet

Hi Jack,
Follow these steps to correct the ethernet:
1. Break into u-boot by resetting the system and hitting any key before the intial countdown finishes.
2. Type the following command: Gregory Gluszek