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From 01/22/2014 to 02/20/2014

02/20/2014

DV 02:39 PM FPGA Development: RE: HPS Memory Controller
Nope, if you connect it to the HPS to FPGA bridge you can treat it more like a register that the code on the HPS reads. You could also use the FPGA to HPS bridge to write to a specific location in memory, though I have no experience with... Daniel Vincelette
01:10 PM FPGA Development: RE: HPS Memory Controller
Hi Dan,
Don't you mean connect it to the FPGA to HPS AXI bridge?
Our input data is processed in the FPGA.
Thanks!
Jack Anonymous
DV 01:03 PM FPGA Development: RE: HPS Memory Controller
At that rate it might be simpler to create a FIFO in the FPGA and connect it to the light weight HPS to FPGA bridge. Then have the HPS poll that register continuously. We've run that interface at 100Mhz, mainly for control and status reg... Daniel Vincelette

02/19/2014

05:33 PM FPGA Development: RE: HPS Memory Controller
Also, I'm trying to by pass the SGDMA dispatcher and use the write master directly.
Jack Anonymous
05:32 PM FPGA Development: RE: HPS Memory Controller
Hi Dan,
Our data is coming in at about 40 MHz,
Jack Anonymous
DV 04:57 PM FPGA Development: RE: HPS Memory Controller
Hi Jack,
Looking in the SGDMA dispatcher core user guide, it appears that if you use the extended descriptors you can set the write stride to zero, which would allow you to continuous write to the same address.
What is your require... Daniel Vincelette
04:33 PM FPGA Development: RE: HPS Memory Controller
Hi Dan,
Regarding the SGDMA Write Master Core. I looked through the document for this core and it doesn't give any information on these questions.
For the write command sink port, what exactly is the purpose of "write stride" (91-7... Anonymous
DV 03:40 PM FPGA Development: RE: HPS Memory Controller
Jack,
We do not currently have an example that uses a non-packetized Avalon stream. There should be an option in the SGDMA controller to disable packets but we haven't tried to use it.
Dan Daniel Vincelette
03:22 PM FPGA Development: RE: HPS Memory Controller
Hi,
Do you have any write to HPS memory examples where I can send data into the memory in a continuous stream rather than a packet at a time?
Thanks!
Jack Anonymous

02/13/2014

DV 03:02 PM FPGA Development: RE: Signal Tap & JTAG FPGA Programming
Glad to hear you got it working.
Dan Daniel Vincelette
03:01 PM FPGA Development: RE: Signal Tap & JTAG FPGA Programming
Hi Dan,
Yes it works with the rbf file and it works when I program it in Linux. No problems there.
I managed to get it programming with the JTAG.
Thanks again for your help!
Jack
 Anonymous
DV 01:58 PM FPGA Development: RE: Signal Tap & JTAG FPGA Programming
Hi Jack,
I've just created a wiki page for the steps that it takes to program the FPGA using the USB-Blaster, would you mind trying that and telling me where it fails and at what percent of the progress bar it fails at?
The link is... Daniel Vincelette
12:58 PM FPGA Development: Signal Tap & JTAG FPGA Programming
Hi,
I'm raised the issue before regarding programming the FPGA with JTAG.
I have tried programming via JTAG, the driver is installed and Quartus does recognize it, but it always fails when I attempt to program it.
I need to use ... Anonymous

02/07/2014

JL 11:29 AM Software Development: Bitbake Error
I am running into the current error while running bitbake:
jliriano@ArmDev:~/yocto/build$ bitbake u-boot
ERROR: Execution of event handler 'external_linaro_toolchain_version_handler' failed
Traceback (most recent call last):
Fil... Julio Liriano

02/03/2014

AB 03:55 PM Software Development: Yocto Plug-In Python.exe Error
Posting on behalf of a customer: Alexander Block

01/30/2014

GG 10:01 AM FPGA Development: RE: Ethernet
Edited my response. Good eye Dave. Thanks! Gregory Gluszek
DR 09:31 AM FPGA Development: RE: Ethernet
Greg,
Only 2 "e"s in setenv, not three... Jack probably knows that, but just to be clear...
Dave
 David Rice
GG 09:10 AM FPGA Development: RE: Ethernet
Hi Jack,
Follow these steps to correct the ethernet:
1. Break into u-boot by resetting the system and hitting any key before the intial countdown finishes.
2. Type the following command: Gregory Gluszek

01/29/2014

06:48 PM FPGA Development: RE: Ethernet Rev B
Hi,
I just received your rev B module. We noticed that the ethernet doesn't work on this revision at all. Is there another way to transfer my fpga and programming file to the linux OS. uBoot will do the FPGA but will it take care of m... Anonymous

01/27/2014

DV 12:56 PM FPGA Development: RE: Load FPGA Timeout Error
Hi Jack,
I'm not sure what else to try other than trying to program the FPGA through a JTAG pod, which I believe you said you don't have, or sending it back for an RMA.
Dan Daniel Vincelette

01/24/2014

01:57 PM FPGA Development: RE: Load FPGA Timeout Error
Hi Dan,
I did what Adam suggested and it made no difference. I tried it without anything plugged in and still nothing.
Jack Anonymous
DV 01:21 PM FPGA Development: RE: Load FPGA Timeout Error
Currently I do not believe that is the case, seeing as this problem is happening in both uboot and linux.
Have you tried programming the FPGA without anything else plugged in (such as a HSMC card) and setting the MSEL like Adam advise... Daniel Vincelette
12:28 PM FPGA Development: RE: Load FPGA Timeout Error
Could this be a OS issue that's causing it?
Can some one direct me the exact link where I can download the img file?
Jack Anonymous

01/22/2014

AD 03:37 PM FPGA Development: RE: Load FPGA Timeout Error
Your MSEL is currently 00000. Try changing S100-position3 to OFF to get an MSEL[4:0] of 00100. This will change the power-on reset delay to Standard instead of Fast.
To read the switch settings, note the white labels in silkscreen on... Adam Dziedzic
DV 03:11 PM FPGA Development: RE: Load FPGA Timeout Error
Looking through the uboot source code it seems that the HPS is not able to set the FPGA into a reset mode. Which could possibly be a hardware issue. One last test is if you have an HSMC board connected, unplug it and try to load the FPGA... Daniel Vincelette
02:57 PM FPGA Development: RE: Load FPGA Timeout Error
correct Anonymous
DV 02:56 PM FPGA Development: RE: Load FPGA Timeout Error
Is the following the full error you received? Daniel Vincelette
02:34 PM FPGA Development: RE: Load FPGA Timeout Error
Yes Anonymous
DV 02:33 PM FPGA Development: RE: Load FPGA Timeout Error
was this from the **run fpgaload**? Daniel Vincelette
02:31 PM FPGA Development: RE: Load FPGA Timeout Error
Hi Dan,
I got an error: Failed with error code -1.
Jack Anonymous
DV 02:29 PM FPGA Development: RE: Load FPGA Timeout Error
Hi Jack,
This needs to be run during uboot, which you get to by pressing any key during the first 5 seconds of start up. If you are able to load it through uboot then that should factor out a hardware issue.
Dan Daniel Vincelette
02:13 PM FPGA Development: RE: Load FPGA Timeout Error
Hi Dan,
The Linux OS on the board doesn't have run and saveenv. I tried to update it, but it doesn't have the apt-get command either.
Cheers,
Jack Anonymous
DV 01:33 PM FPGA Development: RE: Load FPGA Timeout Error
Daniel Vincelette
12:59 PM FPGA Development: RE: Load FPGA Timeout Error
Hi Dan,
Regarding the uboot procedure, I have never worked with uboot before and the instructions on rocketboard is not very specific as to how to set it up. Could you provide some help on this please?
Thanks again for all your hel... Anonymous
12:33 PM FPGA Development: RE: Load FPGA Timeout Error
Hi Adam,
I'm not sure what the default positions for the MSEL or which of the switches on board are for the MSEL. So here's a picture.
Thanks,
Jack Anonymous
AD 12:23 PM FPGA Development: RE: Load FPGA Timeout Error
Hi Jack,
Please check the MSEL dip switches. These should be set to FPPx16 or FPPx32 for the FPGA Manager to be able to load the FPGA. Those pins are read at power-on. MSEL details can be found in:
Table 7-2 of:
http://www.alte... Adam Dziedzic
12:07 PM FPGA Development: RE: Load FPGA Timeout Error
Hi Dan,
The same issue still occurs after power cycling.
I'm wondering if it's a hardware issue.
Jack Anonymous
DV 10:43 AM FPGA Development: RE: Load FPGA Timeout Error
Hi Jack,
We have not seen this issue yet. If you power cycle the board did this issue still occur?
Dan Daniel Vincelette
 

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