Activity
From 12/16/2013 to 01/14/2014
01/09/2014
- ND 08:50 AM FPGA Development: RE: I/O voltage
- Thanks, very useful info. Will give it a try over the next couple of weeks.
Nigel.
01/08/2014
- AD 04:57 PM FPGA Development: RE: I/O voltage
- Hi Nigel,
Below you will find the details to support additional IO standards. I believe this covers all the necessary details...
h2. MityARM-5CSX VIO Support
h3. VCCPD Power and Support for +3.0 or +3.3V Standards
The I/O ba... - ND 01:53 PM FPGA Development: RE: I/O voltage
- Any update on whether the dev kit can be configured for 3.3v I/O?
Thanks,
Nigel.
12/23/2013
- ND 10:46 AM FPGA Development: RE: I/O voltage
- No problem, it can wait a while.
Sounds like the SOM may have been catered for. Any thoughts on the dev kit or do you need to wait for the designer to get back?
Thanks.
Nigel. - MW 09:03 AM FPGA Development: RE: I/O voltage
- Hi Nigel,
The best guy to answer this question is on break this week and a good chunk of next week, can you wait for an answer?
Looking at the schematic, VCCPD3B4A is driven by a small compare/mux circuit that selects 2.5 V if VIO_... - I would like to interface the MityARM-5C SX dev kit to an existing piece of equipment for evaluation purposes, however this equipment uses 3.3v I/O. Is seems from the schematic that the bank I/O for the FPGA signals on the HSMC interface...
12/16/2013
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12:23 PM
FPGA Development: RE: HPS Memory Controller
- Hi Dan,
We figured it out last week. So we are fine with this for now.
Jack