Mity CPU Platforms » MitySOM-5CSX Altera Cyclone V

12/23/2013

ND 10:46 AM FPGA Development: RE: I/O voltage

No problem, it can wait a while.
Sounds like the SOM may have been catered for. Any thoughts on the dev kit or do you need to wait for the designer to get back?
Thanks.
Nigel. Nigel Doe

MW 09:03 AM FPGA Development: RE: I/O voltage

Hi Nigel,
The best guy to answer this question is on break this week and a good chunk of next week, can you wait for an answer?
Looking at the schematic, VCCPD3B4A is driven by a small compare/mux circuit that selects 2.5 V if VIO_... Michael Williamson

ND 08:15 AM FPGA Development: I/O voltage

I would like to interface the MityARM-5C SX dev kit to an existing piece of equipment for evaluation purposes, however this equipment uses 3.3v I/O. Is seems from the schematic that the bank I/O for the FPGA signals on the HSMC interface... Nigel Doe

12/16/2013

12:23 PM FPGA Development: RE: HPS Memory Controller

Hi Dan,
We figured it out last week. So we are fine with this for now.
Jack Anonymous

12/12/2013

05:17 PM FPGA Development: RE: HPS Memory Controller

Hi Dan,
I'm still confused about this. Would it be possible to provide an example of multiple packets?
For example two packets each with a counter.
Thanks!
Jack Anonymous

12/10/2013

DV 06:36 PM FPGA Development: RE: HPS Memory Controller

The descriptors are pushed onto a descriptor FIFO that the dispatcher reads from to start each transaction. So with setting the go bit, the descriptor will be written on to this FIFO.
To send multiple packets you will have to push mul... Daniel Vincelette

05:18 PM FPGA Development: RE: HPS Memory Controller

Hi Dan,
Is there any timing diagram with the SGDMA? I want to control some of the signals directly in the FPGA.
Thanks!
Jack Anonymous

04:49 PM FPGA Development: RE: HPS Memory Controller

Hi Dan,
I'm confused about this, does the Go signal go to "0" after each transfer such that I have to toggle it back to "1"?
I tried doing that but it didn't work.
Could you provide exactly what needs to be done to send multiple... Anonymous

DV 04:28 PM FPGA Development: RE: HPS Memory Controller

Yes, you need to set the go bit so the dispatcher knows that the descriptor is ready to be read.
Dan Daniel Vincelette

12:17 PM FPGA Development: RE: HPS Memory Controller

Hi again,
Just reading through the document. Do I have to set GO to '1' each time I update the descriptor?
Thanks!
Jack Anonymous

12:12 PM FPGA Development: RE: HPS Memory Controller

Hi Dan,
I'm changing the write address in the descriptor in the VHDL. But it's still only writing to the first address and not writing to the subsequent address that I changed to. Is there something else that I have to do to update th... Anonymous

12/09/2013

DV 03:53 PM FPGA Development: RE: HPS Memory Controller

Hi Jack,
Park Writes – When set the dispatcher will continue to reissue the same descriptor to the write
master when no other descriptors are buffered.
Yup, the address is part of the descriptor along with control signals.
For ... Daniel Vincelette

03:37 PM FPGA Development: RE: HPS Memory Controller

Hi Dan,
What's parked write? Is that just writing to one address only?
Is the descriptor like an address line?
For our project, we have a signal (Data Ready) and whenever it goes to zero, there is a 16 bit data that comes in. I ... Anonymous

DV 02:26 PM FPGA Development: RE: HPS Memory Controller

Hi Jack,
Each packet needs its own descriptor, unless you are using parked writes. The descriptor is what tells the SGDMA component where to write that packet to, so the second packet will stall until another descriptor is pushed onto... Daniel Vincelette

02:15 PM FPGA Development: RE: HPS Memory Controller

Hi,
Just a question with regarding sending these data as a package.
I know that the data in the package will be stored consecutively starting from the starting address.
But if that package is ended, and I start a second package ... Anonymous