Mity CPU Platforms » MitySOM-5CSX Altera Cyclone V

12/10/2013

DV 06:36 PM FPGA Development: RE: HPS Memory Controller

The descriptors are pushed onto a descriptor FIFO that the dispatcher reads from to start each transaction. So with setting the go bit, the descriptor will be written on to this FIFO.
To send multiple packets you will have to push mul... Daniel Vincelette

05:18 PM FPGA Development: RE: HPS Memory Controller

Hi Dan,
Is there any timing diagram with the SGDMA? I want to control some of the signals directly in the FPGA.
Thanks!
Jack Anonymous

04:49 PM FPGA Development: RE: HPS Memory Controller

Hi Dan,
I'm confused about this, does the Go signal go to "0" after each transfer such that I have to toggle it back to "1"?
I tried doing that but it didn't work.
Could you provide exactly what needs to be done to send multiple... Anonymous

DV 04:28 PM FPGA Development: RE: HPS Memory Controller

Yes, you need to set the go bit so the dispatcher knows that the descriptor is ready to be read.
Dan Daniel Vincelette

12:17 PM FPGA Development: RE: HPS Memory Controller

Hi again,
Just reading through the document. Do I have to set GO to '1' each time I update the descriptor?
Thanks!
Jack Anonymous

12:12 PM FPGA Development: RE: HPS Memory Controller

Hi Dan,
I'm changing the write address in the descriptor in the VHDL. But it's still only writing to the first address and not writing to the subsequent address that I changed to. Is there something else that I have to do to update th... Anonymous

12/09/2013

DV 03:53 PM FPGA Development: RE: HPS Memory Controller

Hi Jack,
Park Writes – When set the dispatcher will continue to reissue the same descriptor to the write
master when no other descriptors are buffered.
Yup, the address is part of the descriptor along with control signals.
For ... Daniel Vincelette

03:37 PM FPGA Development: RE: HPS Memory Controller

Hi Dan,
What's parked write? Is that just writing to one address only?
Is the descriptor like an address line?
For our project, we have a signal (Data Ready) and whenever it goes to zero, there is a 16 bit data that comes in. I ... Anonymous

DV 02:26 PM FPGA Development: RE: HPS Memory Controller

Hi Jack,
Each packet needs its own descriptor, unless you are using parked writes. The descriptor is what tells the SGDMA component where to write that packet to, so the second packet will stall until another descriptor is pushed onto... Daniel Vincelette

02:15 PM FPGA Development: RE: HPS Memory Controller

Hi,
Just a question with regarding sending these data as a package.
I know that the data in the package will be stored consecutively starting from the starting address.
But if that package is ended, and I start a second package ... Anonymous

12/06/2013

DV 03:14 PM FPGA Development: RE: HSMC to GPIO

Hi Jack,
The 5CSX dev board follows the Altera defined pinout for HSMC so that should work.
Dan Daniel Vincelette

03:00 PM FPGA Development: HSMC to GPIO

Hi,
Is HSMC on base board laid out the same pin out as this particular Terasic daughter board (this is what Altera follows in their layout)
I attached the manual for the daughterboard.
Thanks!
Jack Anonymous

12/05/2013

06:14 PM FPGA Development: RE: HPS Memory Controller

Beautiful Work! Thank you so much!
Jack Anonymous

05:57 PM FPGA Development: RE: HPS Memory Controller

O of course! Can't believe something simple like that slipped my mind.
Thank you so much! Hope this works!
Jack Anonymous

DV 05:51 PM FPGA Development: RE: HPS Memory Controller

Hi Jack,
1) Hmm, I believe that error is from qsys generate not being run. Let me know if after running generate if that error still comes up.
2) Yes that is correct, it just needs follow the "Avalon Stream Standard":http://www.alt... Daniel Vincelette

05:35 PM FPGA Development: RE: HPS Memory Controller

Hi Dan,
A couple of issues:
1. I am having trouble compiling the code. It's returning warnings and errors like such:
Warning (125092): Tcl Script File mityarm_5csx_dev_board/synthesis/mityarm_5csx_dev_board.qip not found
Error ... Anonymous

DV 03:34 PM FPGA Development: RE: HPS Memory Controller

Jack,
I have created a new wiki section and have added the hps ddr example there. "LINK":http://redmine.criticallink.com/redmine/projects/mityarm-5cs/wiki/Writing_to_HPS_Memory
Dan Daniel Vincelette

12/04/2013

DV 08:23 PM FPGA Development: RE: HPS Memory Controller

Hey Jack,
My plan is to get it up Thursday afternoon. I currently have the FPGA side done but need to finish up the linux side and test it.
Dan Daniel Vincelette

05:18 PM FPGA Development: RE: HPS Memory Controller

Hi Dan,
When would you be able to make the examples available?
Thanks!
Jack Anonymous

12/02/2013

04:28 PM FPGA Development: RE: FPG DDR3 Memory Pin Assignment

Hi Dan,
We would like to use the HPS DDR as well, but as you can see from my numerous posts, we are really stuck on memory write to multiple addresses. So while you guys are preparing an example for writing to the HPS DDR, we will hav... Anonymous

DV 04:17 PM FPGA Development: RE: FPG DDR3 Memory Pin Assignment

Hi Jack,
Hmm, are you using the DDR SDRAM Controller with UniPHY in your QSYS project?
Also with this first release of the 5CSX SOM there is a special hardware modification that is needed in order to get the FPGA DDR to work, which... Daniel Vincelette

02:34 PM FPGA Development: RE: FPG DDR3 Memory Pin Assignment

Hi Dan,
I don't see the TCL file that you are referring to. All the tcl files that I have are for HPS DDR not FPGA except for the one that you attached.
I attached the a print screen showing all the files.
Jack Anonymous

DV 02:30 PM FPGA Development: RE: FPG DDR3 Memory Pin Assignment

Hi Jack,
Did you also run the IO Standard TCL file generated by the tools?
Dan Daniel Vincelette

02:25 PM FPGA Development: RE: FPG DDR3 Memory Pin Assignment

Hi Dan,
I ran the tcl script that you attached on this thread.
But when I tried to compile, it gives me errors like the following:
Error (169026): Pin FPGA_DDR_A[0] is incompatible with I/O bank 5A. It uses I/O standard 2.5 V, w... Anonymous

DV 02:21 PM FPGA Development: RE: FPG DDR3 Memory Pin Assignment

Hi Jack,
The IO Standard TCL file should be auto-generated by the tools.
To run it from Quartus:
1) Go to Tools->TCL Scripts
2) In the TCL Scripts window you should see multiple tcl scripts, there should be one that looks like mi... Daniel Vincelette

12:32 PM FPGA Development: RE: FPG DDR3 Memory Pin Assignment

Hi Dan,
Could you provide the TCL file for the IO Standard as well please?
Thanks!
Jack Anonymous

DV 10:52 AM FPGA Development: RE: FPG DDR3 Memory Pin Assignment

Hi Jack,
I have attached a TCL file that will setup the pin assignments for the FPGA DDR.
Dan Daniel Vincelette

11:31 AM FPGA Development: RE: Link Down

Hi Dan,
It happens while it's idling and booting up.
Thanks!
Jack Anonymous

DV 11:05 AM FPGA Development: RE: Link Down

Hi Jack,
Is this while the dev kit is just idling in linux? Or is this just during boot up?
Dan Daniel Vincelette

DV 11:03 AM FPGA Development: RE: HPS Memory Controller

Hi Jack,
Have you taken the SDRAM FPGA port out of reset? The register is called hps.sdr.ctrlgrp.fpgaportrst, the description can be found in "HPS Addressmap":http://www.altera.com/literature/hb/cyclone-v/hps.html#hps.sdr.ctrlgrp.fpga... Daniel Vincelette

11/28/2013

04:57 PM FPGA Development: FPG DDR3 Memory Pin Assignment

Hi,
Can you please provide the pin assignment for the optional FPGA DDR3 memory please?
Thanks!
Jack Anonymous

11/27/2013

05:07 PM FPGA Development: RE: HPS Memory Controller

I read through the section for the Cyclone V on the HPS-FPGA AXI and the manual for the SDRAM that we are using but I can't find any info so I would appreciate your help.
I can get data stored in one location of the memory. But when I... Anonymous

11/26/2013

04:37 PM FPGA Development: RE: HPS Memory Controller

Hi,
Can someone please get back to me on this?
Thanks!
Jack Anonymous

11/22/2013

GG 05:01 PM FPGA Development: RE: Quartus II Subscription Edition Error

Hi Jack,
Perhaps the project was corrupted when you upgraded it to the 13.1 tools. I've attached a copy of the project that has been successfully upgraded to build in the 13.1 tools.
Let us know if you have any issues.
Thanks... Gregory Gluszek

03:29 PM FPGA Development: RE: HPS Memory Controller

Hi Mike,
Can you provide for me the exact product number for the Micron SDRAM on board. I need information on the timing parameters for those memories.
Thanks!
Jack Anonymous

11/21/2013

02:10 PM FPGA Development: RE: Quartus II Subscription Edition Error

Hi Greg,
I am using 13.1 Quartus, and I ran the script that you recommended and the error that I sent you was what I got after I ran the script. So it's not from the compiling part, but just the script.
Thanks!
Jack Anonymous

GG 02:08 PM FPGA Development: RE: Quartus II Subscription Edition Error

Hi Jack,
Are those the same errors you were receiving before? And typically when Quartus reports an error there is a plus symbol next to it that you can use to expand the error message and get more details. Could you provide us with ... Gregory Gluszek

12:35 PM FPGA Development: RE: Quartus II Subscription Edition Error

I tried running the tcl script and it didn't work.
The errors are:
Error: Quartus II 64-Bit TimeQuest Timing Analyzer was unsuccessful. 1 error, 0 warnings
Error: Peak virtual memory: 368 megabytes
Anonymous

GG 09:02 AM FPGA Development: RE: Quartus II Subscription Edition Error

Hi Jack,
What version of the Quartus tools are you using?
That project was built with the 13.0 sp1 tools. If you've updated it to the 13.1 tools you probably need to run the hps_sdram_p0_pin_assignments.tcl. Select Tools -> Tcl Sc... Gregory Gluszek

MW 07:05 AM FPGA Development: RE: HPS Memory Controller

HI Jack,
I suggest you head over to the "Cyclone V Documentation page":http://www.altera.com/literature/lit-cyclone-v.jsp Altera web site for this information.
The documentation is extensive, and should provide the information you ... Michael Williamson

11/20/2013

06:25 PM FPGA Development: HPS Memory Controller

Hi,
Could you guys provide some documents and timing diagrams for the HPS memory controller?
Thanks!
Jack Anonymous

04:53 PM FPGA Development: Link Down

Hi again,
I have the ethernet connected to the development kit, but on the console it kept on giving me the following"
libphy: stmmac-0:03 - Link is Up - 1000/Full
libphy: stmmac-0:03 - Link is Dowwn
Repeated for a few seconds. B... Anonymous

03:51 PM FPGA Development: Quartus II Subscription Edition Error

Hi,
I am using the mityarm_5csx_dev_board project that you guys have. If I use the web edition of quartus to run it, everything is fine, but if I use the subscription edition of quartus ii I get some errors.
First of all, when I op... Anonymous

11/19/2013

05:49 PM FPGA Development: Ethernet

Hi,
How can I configure the FPGA such that the ethernet will still be functioning after I program it. I notice that the ethernet is down after I load the fpga.
Cheers,
Jac Anonymous

MW 05:25 PM FPGA Development: RE: Clock

There is a 25 Mhz clock brought in on the main HPS_CLK1 input (pin E20). It's actually defined in the Qsys HPS component of the reference project. Qsys automatically connects the HPS clocks during the build process. You can route this... Michael Williamson

05:18 PM FPGA Development: Clock

Hi,
Where is the clock on the MityArm?
I am using your mityarm_5csx_dev_board project, and it's not there. Could you provide me the pin assignment for your clock please?
Thanks!
Jack Anonymous

11/18/2013

MW 05:04 PM FPGA Development: RE: Unable to access Linux

Hi Jack,
We haven't trying using an Altera MMK, we instead us the USB Blaster or the USB Blaster II directly. Is it possible that the Altera MMK is holding the reset pin active?
You can load the FPGA via an Raw Binary File without... Michael Williamson

04:38 PM FPGA Development: Unable to access Linux

Hi,
I am having trouble accessing the Linux system on the SD card, when the MityARM is connected to the PC, meaning that I can't access on putty. However, when it's not connected to the PC via the programmer board (Altera MMK), I can ... Anonymous

MW 05:01 PM FPGA Development: RE: Input/Output interfacing

Hi Rich,
You need to be careful with the pin assignments. If you change an assignment that is by default controlled by the HPS subsystem to FPGA fabric (or vice-versa) you will need to regenerate the Altera "Pre-Loader" (first stage ... Michael Williamson

MW 04:57 PM FPGA Development: RE: FPGA - HPS DDR Memory

Hi Jack,
I would recommend using Qsys and exporting the FPGA->HPS DDRAM bridges. Then if you create an Avalon memory mapped controller (spec including the timing diagrams can be found "here":http://www.altera.com/literature/manual/mn... Michael Williamson

04:42 PM FPGA Development: FPGA - HPS DDR Memory

Hi,
I need to design system where I store input data to the memory via the FPGA, and then export it out to my computer through the HPS.
My only problem is that I am not very familiar with using the AXI bridge. Can someone please pr... Anonymous

11/14/2013

RB 02:39 PM FPGA Development: RE: Input/Output interfacing

Thanks Mike,
I was able to export the signals I wanted and they now show up in Pin Planner.
Is it in general ok to retask signals in the 5CSX_IO class?
For example, I see that on Module Pin Number 60 corresponding to CYCLONE pin AH2... Rich Bagdazian

11/13/2013

MW 01:41 PM FPGA Development: RE: Input/Output interfacing

The FPGA ball numbers can be mapped to the edge connector via Table 7 in the "datasheet":http://www.mitydsp.com/images/upload/File/MityARM-5CSX-Datasheet.pdf.
The devkit baseboard schematic is "here":http://support.criticallink.com/re... Michael Williamson

11/12/2013

RB 07:03 PM FPGA Development: RE: Input/Output interfacing

Also, I don't know if I have seen a file which shows which physical pins on the FPGA end up on which physical connectors/pins on the carrier board.
Can you point me in the right direction?
Thanks! Rich Bagdazian

RB 07:01 PM FPGA Development: RE: Input/Output interfacing

Hi Dan
Yes, I have done exactly as you described.
I haven't worked with the Pin Planner as of yet, so I'll take a look at that tomorrow.
So if I understand correctly, after I do a successfule Analysis and Synthesis step, the signals... Rich Bagdazian

DV 05:49 PM FPGA Development: RE: Input/Output interfacing

Hi Richard,
I'm guessing you've created a component with a conduit for these external signals and you've exported this conduit through qsys to your top level entity, is this assumption correct? If it is then you can use the pin planne... Daniel Vincelette

RB 04:47 PM FPGA Development: Input/Output interfacing

I have built a custom component in QSYS as a memory-mapped avalon slave and been able to interface it
correctly so that I can communicate with it via the ARM processor as expected. This module also provides
some I/O signals that I want... Rich Bagdazian