Mity CPU Platforms » MitySOM-5CSX Altera Cyclone V

11/14/2013

RB 02:39 PM FPGA Development: RE: Input/Output interfacing

Thanks Mike,
I was able to export the signals I wanted and they now show up in Pin Planner.
Is it in general ok to retask signals in the 5CSX_IO class?
For example, I see that on Module Pin Number 60 corresponding to CYCLONE pin AH2... Rich Bagdazian

11/13/2013

MW 01:41 PM FPGA Development: RE: Input/Output interfacing

The FPGA ball numbers can be mapped to the edge connector via Table 7 in the "datasheet":http://www.mitydsp.com/images/upload/File/MityARM-5CSX-Datasheet.pdf.
The devkit baseboard schematic is "here":http://support.criticallink.com/re... Michael Williamson

11/12/2013

RB 07:03 PM FPGA Development: RE: Input/Output interfacing

Also, I don't know if I have seen a file which shows which physical pins on the FPGA end up on which physical connectors/pins on the carrier board.
Can you point me in the right direction?
Thanks! Rich Bagdazian

RB 07:01 PM FPGA Development: RE: Input/Output interfacing

Hi Dan
Yes, I have done exactly as you described.
I haven't worked with the Pin Planner as of yet, so I'll take a look at that tomorrow.
So if I understand correctly, after I do a successfule Analysis and Synthesis step, the signals... Rich Bagdazian

DV 05:49 PM FPGA Development: RE: Input/Output interfacing

Hi Richard,
I'm guessing you've created a component with a conduit for these external signals and you've exported this conduit through qsys to your top level entity, is this assumption correct? If it is then you can use the pin planne... Daniel Vincelette

RB 04:47 PM FPGA Development: Input/Output interfacing

I have built a custom component in QSYS as a memory-mapped avalon slave and been able to interface it
correctly so that I can communicate with it via the ARM processor as expected. This module also provides
some I/O signals that I want... Rich Bagdazian

10/18/2013

RB 12:10 PM Software Development: RE: Design examples

Right. After a little digging I figured out that QSYS does the heavy lifting of
configuring the protocol glue logic to implement their various standard interfaces
like avalon and then creates a top level hdl file with the appropriate ... Rich Bagdazian

BD 10:35 AM Software Development: RE: Design examples

I'm glad you're over the hurdle, Rich. We don't have a formal tutorial yet, other than the sample project included with the virtual machine image.
This sample FPGA project (and associated directory structure) is located here:
~/proj... Bob Duke

DV 10:20 AM Software Development: RE: Moving rbf file from host to dev-board

Hi Rich,
You'll need to SCP the RBF over, I'm pretty sure FTP wasn't enabled by default. But I believe you will need to set a root password on your board in order to SCP files to it.
To set a root password use the passwd command on... Daniel Vincelette

10/17/2013

RB 06:29 PM Software Development: Moving rbf file from host to dev-board

I have created a new rbf file with some custom logic added which I built using QSYS,
and converted from SOF format to RBF format as required.
I attempted to use an ftp client (Filezilla) to move the rbf file to the dev board
and the c... Rich Bagdazian

RB 06:26 PM Software Development: RE: Design examples

Ok, I was able to build a system with a new component that I created in QSYS
and added some custom VHDL logic to for testing purposes. So I think I'm
over the hurdle. Rich Bagdazian