Mity CPU Platforms » MityDSP (TI TMS320C6xxx Based Products)

12/12/2013

MW 06:56 PM FPGA Development: RE: ASADSn / ASREn pin loc

EMIF_ASADS# is routed to Y16, bank 4.
-Mike
Michael Williamson

LC 06:51 PM FPGA Development: ASADSn / ASREn pin loc

Hi,
Is the EMIFA signal ASADSn/ASREn routed to the FPGA? If so, what is the pin location?
I'm using the MityDSP-Pro, 6455-JE-3X5-R.
Cheers,
Leon Craven Leon Craven

LC 05:48 PM FPGA Development: RE: Additional Address Lines EA[19 downto 10] pin loc

Thanks Leon Craven

MW 05:47 PM FPGA Development: RE: Additional Address Lines EA[19 downto 10] pin loc

Hi Leon,
Here are the rest of the EMIF_AEA pin assignments.
-Mike
| NET | FPGA PIN | FPGA BANK |
| EMIF_AEA10 | AA9 | 5 |
| EMIF_AEA11 | AC11 | 5 |
| EMIF_AEA12 | AE12 | 5 |
| EMIF_AEA13 | AC10 | 5 ... Michael Williamson

LC 04:48 PM FPGA Development: RE: Additional Address Lines EA[19 downto 10] pin loc

Hi,
Sorry, I'm using the MityDSP-Pro, 6455-JE-3X5-R.
Cheers,
Leon Leon Craven

MW 07:08 AM FPGA Development: RE: Additional Address Lines EA[19 downto 10] pin loc

Hi Leon,
While module are you using? Do you have a model number or a part number?
-Mike
Michael Williamson

12/11/2013

LC 11:08 PM FPGA Development: Additional Address Lines EA[19 downto 10] pin loc

Hi,
In the supplied ucf files I can only find pin information for address lines i_emif_aea[9 downto 0]. I would like to use the other address lines. Are they routed to the FPGA? If so what are their pin locations on the FPGA.
Regar... Leon Craven