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From 11/12/2013 to 12/11/2013

12/11/2013

LC 11:08 PM FPGA Development: Additional Address Lines EA[19 downto 10] pin loc
Hi,
In the supplied ucf files I can only find pin information for address lines i_emif_aea[9 downto 0]. I would like to use the other address lines. Are they routed to the FPGA? If so what are their pin locations on the FPGA.
Regar...
Leon Craven
 

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