Activity
From 06/22/2013 to 07/21/2013
07/03/2013
- MW 07:49 AM FPGA Development: RE: How to use the sdram for FPGA and EMIFA bus in MityDSP-Pro board?
- Hello Mr. Feng,
I am attaching the DDR MIG Test Bench that we originally used to validate the FPGA DDR connection. At a minimum, you should find the FPGA connections in the UCF contained within.
The MIG project for this is somewha... - Hello,
Our project needs a large mount of data transfer, so I want to know the assignment of pin for sdram of FPGA and the EMIFA address bus(i_emif_aea), I cann't find them in MityDSP-Pro.ucf. will you give me some FPGA demo for them. ...
06/24/2013
- XW 10:09 AM Software Development: RE: MityDSP Pro development kit boot anormally
- Hi Mike, thanks again for your reply.
I tried to regulate the RECONFIG_CLOCKS() to recover the board but the core hungs on the call.
I tried then to set the EMIF frequency to 100MHz with the code in my original post with
@
C6455_PLL... - MW 08:12 AM Software Development: RE: MityDSP Pro development kit boot anormally
- The problem you are having is that the FPGA logic is using the EMIFA clock with a PLL as the main logic clock within the FPGA fabric on the module.
The FPGA fabric is designed to run using a 100 MHz EMIFA clock. When you change the P... - Hello,
I am using the MityDSP-Pro development kit. Recentlly I find the board behaviors strangely.
I was debugging using the CCStudio 5.3, with some command to change the CPU frequency, all
go well. But as soon as I call any firmwir... - XW 07:12 AM Software Development: RE: How to implement the SetOuput function in the tcDspOutputLatch class for DAC application?
- Hi Michael, thanks for your reply.
I am using the MityDSP-PRO Development Kit with the Critical Link provided extention board.
For this board, I dont know which pin to write to select the TLV5610 DAC module.