Mity CPU Platforms » MityDSP (TI TMS320C6xxx Based Products)

03/05/2013

锋曲 11:32 PM FPGA Development: RE: How does DSP configure FPGA program?

Thank you very much Mike, 锋 曲

MW 01:04 PM FPGA Development: RE: How does DSP configure FPGA program?

Here you go. Good luck.
| *FPGA* | *DSP* |
| DONE | GP_7 |
| INIT | GP_6 |
| PROGRAM | GP_1 |
| CCLK | EMIF_AAOEn and EMIF_AAWEn (external and gate) |
| BUSY | EMIF_AARDY |
| D(7..0) | EMIF_AED(7..0) |
| CS | EMIF_ACE2n and E... Michael Williamson

锋曲 10:02 AM FPGA Development: RE: How does DSP configure FPGA program?

Hello mike,
Thank you very much for your reply, I would like to know which pins of DSP are used to configure FPGA, like CCLK,WRITE,DATA[0:7],BUSY,,DONE,INIT,PROGRAM. Because the program framework of our project has been completed, and t... 锋 曲

MW 07:47 AM FPGA Development: RE: How does DSP configure FPGA program?

Hello,
The DSP configures the FPGA using slave parallel select mode (8-bits at a time) using a connection to the EMIFA and a couple of GPIO pins to drive the PROGRAM, CS, and INIT pins to monitor the load status.
Details about para... Michael Williamson

02/27/2013

锋曲 08:21 PM FPGA Development: How does DSP configure FPGA program?

Hello,
I'm using MityDSP-PRO Development Kit to our project, and our DSP is 6455,and FPGA is xc3s4000. I want to know how does DSP configure FPGA program? Does it is the way of picture attached? if so, would you like to tell us the... 锋 曲