Mity CPU Platforms » MityDSP (TI TMS320C6xxx Based Products)

03/05/2013

锋曲 11:32 PM FPGA Development: RE: How does DSP configure FPGA program?

Thank you very much Mike, 锋 曲

MW 01:04 PM FPGA Development: RE: How does DSP configure FPGA program?

Here you go. Good luck.
| *FPGA* | *DSP* |
| DONE | GP_7 |
| INIT | GP_6 |
| PROGRAM | GP_1 |
| CCLK | EMIF_AAOEn and EMIF_AAWEn (external and gate) |
| BUSY | EMIF_AARDY |
| D(7..0) | EMIF_AED(7..0) |
| CS | EMIF_ACE2n and E... Michael Williamson

锋曲 10:02 AM FPGA Development: RE: How does DSP configure FPGA program?

Hello mike,
Thank you very much for your reply, I would like to know which pins of DSP are used to configure FPGA, like CCLK,WRITE,DATA[0:7],BUSY,,DONE,INIT,PROGRAM. Because the program framework of our project has been completed, and t... 锋 曲

MW 07:47 AM FPGA Development: RE: How does DSP configure FPGA program?

Hello,
The DSP configures the FPGA using slave parallel select mode (8-bits at a time) using a connection to the EMIFA and a couple of GPIO pins to drive the PROGRAM, CS, and INIT pins to monitor the load status.
Details about para... Michael Williamson

02/27/2013

锋曲 08:21 PM FPGA Development: How does DSP configure FPGA program?

Hello,
I'm using MityDSP-PRO Development Kit to our project, and our DSP is 6455,and FPGA is xc3s4000. I want to know how does DSP configure FPGA program? Does it is the way of picture attached? if so, would you like to tell us the... 锋 曲

02/21/2013

AT 08:53 AM PCB Development: RE: MityDSP-Pro RGMII voltage

Thank you Alexander Timokhin

MW 08:37 AM PCB Development: RE: MityDSP-Pro RGMII voltage

DVDD15 is connected to 1.5V.
VREFHSTL (for the EMAC RGMII) is set at to 1.5V / 2.
This is a provision to change the 1.5 voltage to 1.8 V, but it would require removal of 1 resistor (0 ohm jumper) and installation of a second on the... Michael Williamson

AT 08:06 AM PCB Development: MityDSP-Pro RGMII voltage

Hello,
RGMII interface from TMS320C6455 DSP MAC can work with either 1.5V or 1.8V power suply.
What RGMII voltage is used on MityDSP-Pro boards (on Hirose expansion connector)?
Thanks,
Alexander
Alexander Timokhin

02/04/2013

MW 08:12 AM FPGA Development: RE: About CE4 CE5 and INT6's pin asisgnment in FPGA

Hello.
CE4 is connected to W15 of the FPGA (Bank 4).
CE5 is connected to AA15 of the FPGA (Bank 4).
GP [6] is connected to the FPGA_INIT_B signal on the FPGA, AC14. There is also an external 1K pullup to 3.3V on this net.
GP [7] i... Michael Williamson

HP 03:02 AM FPGA Development: About CE4 CE5 and INT6's pin asisgnment in FPGA

Hi，
I want to design a sync fifo in the FPGA, which will use a synchronous interface in EMIF. So it is better
to use a separate CE pin other than CE2.
According to the MityDspProSpec.pdf, DSP pins CE2 CE4 CE5 INT4 INT5 INT6 are... Haibo Pang