Mity CPU Platforms » MityDSP (TI TMS320C6xxx Based Products)

02/04/2013

MW 08:12 AM FPGA Development: RE: About CE4 CE5 and INT6's pin asisgnment in FPGA

Hello.
CE4 is connected to W15 of the FPGA (Bank 4).
CE5 is connected to AA15 of the FPGA (Bank 4).
GP [6] is connected to the FPGA_INIT_B signal on the FPGA, AC14. There is also an external 1K pullup to 3.3V on this net.
GP [7] i... Michael Williamson

HP 03:02 AM FPGA Development: About CE4 CE5 and INT6's pin asisgnment in FPGA

Hi，
I want to design a sync fifo in the FPGA, which will use a synchronous interface in EMIF. So it is better
to use a separate CE pin other than CE2.
According to the MityDspProSpec.pdf, DSP pins CE2 CE4 CE5 INT4 INT5 INT6 are... Haibo Pang