Mity CPU Platforms » MityDSP (TI TMS320C6xxx Based Products)

12/13/2012

JL 05:55 PM FPGA Development: RE: Mity-DSP Xilinx JTAG and Walking One Problem

I am using the base model MityDSP-6711 with the XC3S400 FPGA.
By default, I tri-state/make inputs any I/O pins not involved in the current test. The behavior you describe with pulling low
the P8 pin sounds very much like what is ha... Julio Liriano

MW 05:31 PM FPGA Development: RE: Mity-DSP Xilinx JTAG and Walking One Problem

All ones sounds like the FPGA got it's program pin pulled (it was reset). Is it possible you are driving P8 to Low? Or any other pins in your walking pattern? On the MityDSP, driving P8 of the FPGA low will reset the on-board 6711 pro... Michael Williamson

JL 04:56 PM FPGA Development: Mity-DSP Xilinx JTAG and Walking One Problem

I've developed a JTAG test for our mothercard that the Mity DSP plugs into. I use the Xilinx JTAG to the FPGA on the Mity-DSP to walk a
one pattern on a 32-bit data bus to an Altera FPGA on the Mity-DSPs host card. All works smoothly ... Julio Liriano