Activity
From 04/08/2012 to 05/07/2012
04/25/2012
- MW 03:27 PM FPGA Development: RE: JTAG adapter cable question
- Hi Bob,
We don't offer those through our distributors directly at the moment, they are only part of the Devkit BOMS. If you contact Tom Catalino (tom.catalino@criticallink.com) or Bill Halpin (bhalpin@criticallink.com) they can provi... - Where can I buy the adapter cable which goes from the MityDSP-Pro JTAG connector to the TI Debugger?
This is a 14-pin to 16-pin adapter with a cable and small circuit board.
I have one that came with the MDSP-Pro Development Kit, but I...
04/10/2012
- Is this source code available for me to find examples of how the various DSP configuration registers are set?
At the moment, I'm working on the EMIF interface. I'm reverse engineering the configuration by studying the peripheral regi... - DS 12:35 PM Software Development: RE: Does MityGUI run on Windows XP SP3?
- I tried it here and have the same problem also.
Please use 4.0.5 for now and we'll look into this.
Dave
Peter Faill wrote:
> I've run it on a Windows7 machine without any trouble.
> ...
- PF 11:34 AM Software Development: RE: Does MityGUI run on Windows XP SP3?
- Should have mentioned that I ran version 4.0.6 (just downloaded from 'Files').
Peter - I've run it on a Windows7 machine without any trouble.
But when I run in on a XP machine I get the attached error message.
Peter
04/09/2012
- PF 06:52 PM Software Development: RE: MityDSP: dual port memory within FPGA
- Thanks for the quick reply,
Peter - MW 06:51 PM Software Development: RE: MityDSP: dual port memory within FPGA
- If you are referring to the bootloader image, then I think you have it.
Address lines are 1-to-1.
-Mike
- Hi,
I'd like to test the DSP <=> FPGA bus interface by writing to a FPGA scratch address and then reading back the results to confirm success.
From the firmware, I see that there is dual-port dual RAM area that appears to exist for...