Activity
From 01/12/2012 to 02/10/2012
02/08/2012
- DB 11:51 AM PCB Development: RE: AUX I/O Connector location dimensions
- Thanks Mike,
I have Rev 1/Document Revision: Draft – MityDSP-Pro Rev. B dated Nov 15th 2009 of the design guide and it wasn't in that. I guess there must be a later version. Is the only place to get the documents on the web site were ... - MW 10:58 AM PCB Development: RE: AUX I/O Connector location dimensions
- Hi Doug, dorry for the delay.
The information you need should be in the MityDSP-Pro Carrier board design guide, I am attaching a copy of the figure here. Is this what you need?
-Mike
!MityDSP-PRO-Aux_Connector_Location.png! - DB 10:48 AM PCB Development: RE: AUX I/O Connector location dimensions
- I would like to get a reply to my question. I am finishing up my layout and need to place the connector.
Thanks,
Doug
02/03/2012
- It is recommended to use the AUX I/O connector on the MityDSP-Pro on carrier board designs but I can't seem to find any documentation on the location of the connector. Please let me know if it is called out in any of the documentation. I...
01/26/2012
- BC 01:29 PM FPGA Development: RE: Looking for top-level module for FPGA Hands-on exercise for MDSP-Pro
- Oops! I see it there. Thanks, Mike. That'll work.
- MW 12:51 PM FPGA Development: RE: Looking for top-level module for FPGA Hands-on exercise for MDSP-Pro
- Hi Bob,
Is it not included in the hdl.zip download file? (pulse_gen.vhdl)
-Mike
- Is it possible to get the "answer" top-level module for the MDSP Training Day 1: MityDSP FPGA – Hands-on exercise?
This would be very helpful for me in creating my own module for the MityDSP-Pro.
Thanks.
-Bob Clarke
01/18/2012
- BC 11:23 AM FPGA Development: RE: MityDSP-Pro and host board schematics?
- Mike,
thanks. I will take a look at the info there -- it looks like it will answer a number of our questions. I will contact Tom about the module schematics.
-Bob Clarke - MW 08:11 AM FPGA Development: RE: MityDSP-Pro and host board schematics?
- The Mainboard schematics are available in the "Files Tab":http://support.criticallink.com/redmine/projects/dsp-products/files. Please contact Tom Catalino (catalino@criticallink.com) about the module schematics. If he agrees that the p...
01/17/2012
- BC 05:25 PM FPGA Development: RE: Bank switching for different FPGA applications
- Mike,
my plan was to whip up the application but leave the boot loaders in place for both the DSP and FPGA. I assume that this will be ok if I put my application in the first application storage location. I only plan on using a single a... - MW 05:11 PM FPGA Development: RE: Bank switching for different FPGA applications
- Hi Bob,
The only problem with "whipping stuff up from scratch" will be the fact that the bootloader application provided needs to be able to control the bank-switching serial shift register (via the FPGA) per the addressing scheme def... - MW 05:12 PM FPGA Development: RE: MityDSP-Pro and host board schematics?
- Hi Bob,
I am working to post the Motherboard schematics. We may need an NDA or something for the PRO schematics, I will get back to you on that as soon as possible. Sorry for the delay.
-Mike
- Is it possible to get the schematics posted for these boards? As a minimum I would like to get the pin-out for the DSP and the FPGA on the MityDSP-Pro. The motherboard schematics would also be helpful - we're building our application on ...
01/16/2012
- BC 11:01 AM FPGA Development: RE: Bank switching for different FPGA applications
- Mike,
thanks for the info. I understand that you folks have generated a number of cores that should automatically take care of this and other features of the FPGA. Our application is extremely simple and it will be most expedient for me...
01/13/2012
- MW 05:41 PM FPGA Development: RE: Bank switching for different FPGA applications
- I don't know if Tom got you the Developer's Guides or not, but the bank control logic is generated out of the base_module.vhd (which you have the source code for). It basically updates an external serial shift register with the upper ad...
- MW 05:38 PM FPGA Development: RE: MCS file settings
- Hi Bob,
The MCS file generation is pretty straightforward. The real key is to ensure that you float your unused IOB's in the bitstream generation options. Once you have a .bit file that you like, you can run the following command fr...
01/12/2012
- What file/prom settings should I use when creating an MCS file for my application in the MityDSP-Pro.
-Bob Clarke - BC 01:25 PM FPGA Development: RE: Pins used for MityDSP-Pro FPGA bootloader
- Mike,
I think you've answered my questions. We're seeing the FPGA ethernet activate on our MDK host board but that must be in the default application and not in the boot loader. That's good news for us. We will not be using the FPGA eth... - MW 12:45 PM FPGA Development: RE: Pins used for MityDSP-Pro FPGA bootloader
- For other pin usage, you need to consult with the schematic for the host board. The MityDSP-PRO MDK host board schematics should be available. If you don't have them, let me know and I will get them posted.
-Mike
- MW 12:43 PM FPGA Development: RE: Pins used for MityDSP-Pro FPGA bootloader
- Are you designing a new board or trying to use the Development Kit board for the PRO?
If you are designing a new board, then I would recommend using the ethernet MAC and MDIO that is included in the DSP 6455 rather than put the FPGA E... - I'm using the MityDSP-Pro and trying to determine what pins are used by the bootloader so that they don't conflict with my hardware. The "MityDSP-ProTM Carrier Board Design Guide" does not show the Ethernet pins connected to the FPGA, bu...