Activity
From 12/20/2011 to 01/18/2012
01/18/2012
- BC 11:23 AM FPGA Development: RE: MityDSP-Pro and host board schematics?
- Mike,
thanks. I will take a look at the info there -- it looks like it will answer a number of our questions. I will contact Tom about the module schematics.
-Bob Clarke - MW 08:11 AM FPGA Development: RE: MityDSP-Pro and host board schematics?
- The Mainboard schematics are available in the "Files Tab":http://support.criticallink.com/redmine/projects/dsp-products/files. Please contact Tom Catalino (catalino@criticallink.com) about the module schematics. If he agrees that the p...
01/17/2012
- BC 05:25 PM FPGA Development: RE: Bank switching for different FPGA applications
- Mike,
my plan was to whip up the application but leave the boot loaders in place for both the DSP and FPGA. I assume that this will be ok if I put my application in the first application storage location. I only plan on using a single a... - MW 05:11 PM FPGA Development: RE: Bank switching for different FPGA applications
- Hi Bob,
The only problem with "whipping stuff up from scratch" will be the fact that the bootloader application provided needs to be able to control the bank-switching serial shift register (via the FPGA) per the addressing scheme def... - MW 05:12 PM FPGA Development: RE: MityDSP-Pro and host board schematics?
- Hi Bob,
I am working to post the Motherboard schematics. We may need an NDA or something for the PRO schematics, I will get back to you on that as soon as possible. Sorry for the delay.
-Mike
- Is it possible to get the schematics posted for these boards? As a minimum I would like to get the pin-out for the DSP and the FPGA on the MityDSP-Pro. The motherboard schematics would also be helpful - we're building our application on ...
01/16/2012
- BC 11:01 AM FPGA Development: RE: Bank switching for different FPGA applications
- Mike,
thanks for the info. I understand that you folks have generated a number of cores that should automatically take care of this and other features of the FPGA. Our application is extremely simple and it will be most expedient for me...
01/13/2012
- MW 05:41 PM FPGA Development: RE: Bank switching for different FPGA applications
- I don't know if Tom got you the Developer's Guides or not, but the bank control logic is generated out of the base_module.vhd (which you have the source code for). It basically updates an external serial shift register with the upper ad...
- MW 05:38 PM FPGA Development: RE: MCS file settings
- Hi Bob,
The MCS file generation is pretty straightforward. The real key is to ensure that you float your unused IOB's in the bitstream generation options. Once you have a .bit file that you like, you can run the following command fr...
01/12/2012
- What file/prom settings should I use when creating an MCS file for my application in the MityDSP-Pro.
-Bob Clarke - BC 01:25 PM FPGA Development: RE: Pins used for MityDSP-Pro FPGA bootloader
- Mike,
I think you've answered my questions. We're seeing the FPGA ethernet activate on our MDK host board but that must be in the default application and not in the boot loader. That's good news for us. We will not be using the FPGA eth... - MW 12:45 PM FPGA Development: RE: Pins used for MityDSP-Pro FPGA bootloader
- For other pin usage, you need to consult with the schematic for the host board. The MityDSP-PRO MDK host board schematics should be available. If you don't have them, let me know and I will get them posted.
-Mike
- MW 12:43 PM FPGA Development: RE: Pins used for MityDSP-Pro FPGA bootloader
- Are you designing a new board or trying to use the Development Kit board for the PRO?
If you are designing a new board, then I would recommend using the ethernet MAC and MDIO that is included in the DSP 6455 rather than put the FPGA E... - I'm using the MityDSP-Pro and trying to determine what pins are used by the bootloader so that they don't conflict with my hardware. The "MityDSP-ProTM Carrier Board Design Guide" does not show the Ethernet pins connected to the FPGA, bu...
01/11/2012
- The MityDSP-Pro datasheet states the following:
----"Upon reset the Bank Control Logic defaults to bank zero for bootloading support.
----Following bootloading, the bank control logic is controlled by the FPGA. Refer to
----the MityD... - BC 05:39 PM FPGA Development: RE: Xilinx ISE project file for MityDSP-Pro
- Michael,
I'd prefer to use ISE 13, but I'm fine with 10 or 12 also.
Thanks. - MW 05:09 PM FPGA Development: RE: Xilinx ISE project file for MityDSP-Pro
- Which version of the ISE are you planning to use?
- Is it possible to get a Xilinx ISE project file for one of the basic MityDSP-Pro builds? If this is on the disk that came with the board, can you tell me where I should look?
Thanks!
-Bob Clarke - MW 05:24 PM FPGA Development: RE: CE2, CE4, and CE5 addresses
- The FPGA cores stack up on the CE2 address space (0xA0000000). CE3 is reserved for the FLASH memory. CE4 is reserved for customer use (or use that requires different wait states, etc.).
On CE2, each core is designed to use 0x80 [b... - On the 1.2 GHz C6455 version of the MityDSP-Pro using the XC3S4000, what CE2, CE4, and CE5 EMIF address ranges are already used by the DSP/FPGA cores? What future-proof range of addresses do you recommend for "user" code to avoid confli...
- MW 05:08 PM FPGA Development: RE: Using FPGA cores and library
- Hi Bill,
In short, the hardware\fpga\build_spartan3 folder contains netlists of "cores" (IP functional blocks with a corresponding C++ API in the DspCore.lib library in the MDK) that will "plug-in" to the EMIFA Interface and base_modu... - Do you have a big-picture document describing how to use the multiple FPGA "cores" in the "hardware\boot" folder and/or the mcs files in the "\hardware\FPGA_boot" folder and the pinouts they assume at the MityDSP-Pro (C6455) connector? ...
- BD 12:29 PM Software Development: RE: FPGA Interrupts on MityDSP-Pro
- Thanks, that helped.
01/10/2012
- MW 08:09 AM Software Development: RE: Builds and SYS/BIOS questions ...
- Hi,
In order to actually get the DSP running at 1200 MHz, you will need a macro update to <core/DspMacros.h> to support updating the CPU speed PLL settings. Page on the Global settings only gives the DSP/BIOS library routines the inf... - MW 08:05 AM Software Development: RE: FPGA Interrupts on MityDSP-Pro
- There are 2 lines connected between the FPGA and the DSP intended for interrupt use. On the DSP, 2 GPIO pins are used for interrupt handling (GP [4] and GP [5]). On the FPGA, for example in the MityDSP-Pro.vhd boot image top level, the...
- MW 07:16 AM Software Development: RE: SYS/BIOS Version 6.x on the MityDSP-Pro
- We have not ported the MDK libraries from DSP/BIOS 5 to SYS/BIOS 6 primarily because the C level code is largely common between the MityDSP-6711 and the MityDSP-6455 (the Pro) and TI's SYS/BIOS 6 does not support the TMS320C6711 family o...
01/09/2012
- (posted on behalf of a customer)
I am trying to get some documentation on the FPGA/DSP interrupts for the MityDSP-Pro. In the MityDSP-Pro data sheet "MityDSP-PRO Data Sheet" at http://www.mitydsp.com/images/upload/File/MityDSPProSpec...
01/06/2012
- (posted on behalf of a customer)
I had some early errors regarding -mv64+. I was not aware that the c6455 is a "C64x+" device, so some compile errors occurred until I specified "Generic C64x+ Device" in the "Main" tab under the "Gener... - (posted on behalf of a customer)
Can I use the new "SYS/BIOS" (version 6.x??) with the c6455? I would like to start with the latest stuff to slow my obsolescence. If I can use it, do I use the same template file I used for SYS/BIOS? I...
12/28/2011
- TC 08:20 AM PCB Development: RE: FPGA/DSP Interface Details & external interrupts
- Doug -
I will let the technical team answer the question about the external interrupts. However, we will add information in our design guide detailing the interface between the FPGA and DSP, we will get this done as soon as possible.... - (Posted on behalf of a customer)
I am working on designing the carrier interface board for the MityDSP Pro module. I have the carrier design guideline document but I would like to get more details on the DSP board itself. Specifically...
12/23/2011
- MW 09:45 AM PCB Development: RE: MityDSP-Pro FPGA questions ...
- > In the directory labeled “C:\MityDSP\2.10\hardware\FPGA_boot” I see several sub directories that appear to have pre-compiled FPGA bitstreams for various sized FPGA’s of which I am very familiar with having designed with Xilinx for over...
12/22/2011
- TC 11:53 AM PCB Development: RE: MityDSP-Pro FPGA questions ...
- (from Anthony)
Michael,
Thanks for the response. From what you describe it seems that the signals I intend to use are fine the way they are connected up in our schematics, which just leaves us needing to make sure we have the boo...
12/21/2011
- MW 07:16 PM PCB Development: RE: MityDSP-Pro FPGA questions ...
- Hi Tom / Anthony,
I hope this doesn't muddy the waters, but here is some more information: There are actually 3 EMAC interface options available for the MityDSP-PRO module. DSP using 10/100 MII, DSP using Reduced Gigabit MII, and FP... - TC 01:01 PM PCB Development: RE: MityDSP-Pro FPGA questions ...
- ??From the schematics it appears that the evaluation board is connected to both RJ-45 connectors, one goes to the 10/100 signals on the plug-in module DSP EMAC and the other to what appears to be a Gigabit PHY which uses a GEMAC running ...
- AM 11:04 AM PCB Development: RE: MityDSP-Pro FPGA questions ...
- Hello Tom,
I will try posting this to the support forum as well but I need to clear up some confusion Kevin and I were having yesterday as to what we were seeing. But I need to ask some questions to make sure I understand myself what ...