Activity
From 11/30/2011 to 12/29/2011
12/28/2011
- TC 08:20 AM PCB Development: RE: FPGA/DSP Interface Details & external interrupts
- Doug -
I will let the technical team answer the question about the external interrupts. However, we will add information in our design guide detailing the interface between the FPGA and DSP, we will get this done as soon as possible.... - (Posted on behalf of a customer)
I am working on designing the carrier interface board for the MityDSP Pro module. I have the carrier design guideline document but I would like to get more details on the DSP board itself. Specifically...
12/23/2011
- MW 09:45 AM PCB Development: RE: MityDSP-Pro FPGA questions ...
- > In the directory labeled “C:\MityDSP\2.10\hardware\FPGA_boot” I see several sub directories that appear to have pre-compiled FPGA bitstreams for various sized FPGA’s of which I am very familiar with having designed with Xilinx for over...
12/22/2011
- TC 11:53 AM PCB Development: RE: MityDSP-Pro FPGA questions ...
- (from Anthony)
Michael,
Thanks for the response. From what you describe it seems that the signals I intend to use are fine the way they are connected up in our schematics, which just leaves us needing to make sure we have the boo...
12/21/2011
- MW 07:16 PM PCB Development: RE: MityDSP-Pro FPGA questions ...
- Hi Tom / Anthony,
I hope this doesn't muddy the waters, but here is some more information: There are actually 3 EMAC interface options available for the MityDSP-PRO module. DSP using 10/100 MII, DSP using Reduced Gigabit MII, and FP... - TC 01:01 PM PCB Development: RE: MityDSP-Pro FPGA questions ...
- ??From the schematics it appears that the evaluation board is connected to both RJ-45 connectors, one goes to the 10/100 signals on the plug-in module DSP EMAC and the other to what appears to be a Gigabit PHY which uses a GEMAC running ...
- AM 11:04 AM PCB Development: RE: MityDSP-Pro FPGA questions ...
- Hello Tom,
I will try posting this to the support forum as well but I need to clear up some confusion Kevin and I were having yesterday as to what we were seeing. But I need to ask some questions to make sure I understand myself what ...
12/15/2011
- MW 02:35 PM PCB Development: RE: MityDSP-Pro FPGA questions ...
- The bootloader FPGA image included in the file mention provides a basic UART at pins 14 and 16 of the edge connector as you mentioned.
The FPGA_RSV1 and FPGA_RSV2 lines are not driven, unfortunately. They were left floating in the bo...
12/14/2011
- (posted on behalf of a customer)
RS232_TXD SO-DIMM pin 14
RS232_RXD SO-DIMM pin 16
FPGA_RSV1 SO-DIMM pin 21
FPGA_RSV2 SO-DIMM pin 23
Since we are not using anything out of the F...