Mity CPU Platforms » MityDSP-L138 (ARM9 Based Platforms)

07/22/2019

JC 01:34 PM Software Development: RE: Change data between ARM(Linux) - DSP (bare-metal)

Aviv Prital wrote:
> Hi, thanks for reply!
> ...
The dsplink sources are in the 2014 MDK. MDK_2014-01-13/sw/3rdparty/dsplink_linux_1_65_00_03
Syslink can be download here: http://downloads.ti.com/dsps/dsps_public_sw/sdo_sb/targetconte... Jonathan Cormier

07/18/2019

AP 06:00 AM Software Development: RE: Change data between ARM(Linux) - DSP (bare-metal)

Hi, thanks for reply!
Two follow up questions:
Concerning "you may want to look at some of the DSPlink or syslink code" where could I see this code?
Concerning "opening "/dev/mem" and using mmap()": will I be able to read/write to any... Aviv Prital

07/17/2019

JC 03:04 PM Software Development: RE: Change data between ARM(Linux) - DSP (bare-metal)

Note if your writing your own bare-metal communication you may want to look at some of the DSPlink or syslink code as you'll need to do similar things as they do.
Talked with another engineer.
> We have done a couple different thin... Jonathan Cormier

AP 02:05 PM Software Development: RE: Change data between ARM(Linux) - DSP (bare-metal)

Thanks for the prompt reply!
I'm thinking about shared RAM that ARM user space linux driver will be able to mmap in order to write/read to DSP.
Thanks,
Aviv Aviv Prital

JC 02:01 PM Software Development: RE: Change data between ARM(Linux) - DSP (bare-metal)

Could you provide more information on what is suitable for your project? Jonathan Cormier

AP 01:44 PM Software Development: Change data between ARM(Linux) - DSP (bare-metal)

Hi,
I'd like to use MityDSPL138 kit in order to develop ARM(Linux) - DSP (bare-metal) data exchange over shared memory.
As far as I understand TI's DSPLink/SYSLINK rely on RTOS at DSP which is not suitable in my case.
Is there any ex... Aviv Prital

07/08/2019

VP 02:57 PM FPGA Development: Reference Project AnalogExpansionSuite query

Hi,
I have a custom board with
-- MityDspl-138F module (with FPGA)
-- No Ethernet port
-- UART,USB,SD CARD interface
-- ADC5560 and DAC5672 is used.
we have done following steps till date.
-- I have built VM with MityDSP Cr... Vivek Ponnani

VP 10:05 AM Software Development: RE: uPP receive clock lower limitation in SDR (Single Data Rate mode)

Thanks Greg for your reply and sorry for the late reply.
I will forward your response to our FPGA team. They are using reference from AnalogExpansionSuite (from Critical Link).
Initially as I mentioned, we are able to get demodula... Vivek Ponnani