Mity CPU Platforms » MityDSP-L138 (ARM9 Based Platforms)

07/08/2019

VP 02:57 PM FPGA Development: Reference Project AnalogExpansionSuite query

Hi,
I have a custom board with
-- MityDspl-138F module (with FPGA)
-- No Ethernet port
-- UART,USB,SD CARD interface
-- ADC5560 and DAC5672 is used.
we have done following steps till date.
-- I have built VM with MityDSP Cr... Vivek Ponnani

VP 10:05 AM Software Development: RE: uPP receive clock lower limitation in SDR (Single Data Rate mode)

Thanks Greg for your reply and sorry for the late reply.
I will forward your response to our FPGA team. They are using reference from AnalogExpansionSuite (from Critical Link).
Initially as I mentioned, we are able to get demodula... Vivek Ponnani

06/24/2019

GG 04:38 PM Software Development: RE: uPP receive clock lower limitation in SDR (Single Data Rate mode)

Hi Vivek,
I believe the datasheet is saying that regardless of whether the clock is being used as DDR or SDR the rate cannot be set below 4.69 MHz. However, this also seems to be assuming a default CPU clock of 300 MHz. This all see... Gregory Gluszek

06/21/2019

VP 08:05 AM Software Development: uPP receive clock lower limitation in SDR (Single Data Rate mode)

Hi,
I have a custom board with
-- MityDspl-138F module (with FPGA)
-- No Ethernet port
-- UART,USB,SD CARD interface
we have done following steps till date.
-- I have built VM with MityDSP Critical_Link_Unified_VM_14-04_04-2... Vivek Ponnani