Activity
From 06/07/2019 to 07/06/2019
06/24/2019
- GG 04:38 PM Software Development: RE: uPP receive clock lower limitation in SDR (Single Data Rate mode)
- Hi Vivek,
I believe the datasheet is saying that regardless of whether the clock is being used as DDR or SDR the rate cannot be set below 4.69 MHz. However, this also seems to be assuming a default CPU clock of 300 MHz. This all see...
06/21/2019
- Hi,
I have a custom board with
-- MityDspl-138F module (with FPGA)
-- No Ethernet port
-- UART,USB,SD CARD interface
we have done following steps till date.
-- I have built VM with MityDSP Critical_Link_Unified_VM_14-04_04-2...