Mity CPU Platforms » MityDSP-L138 (ARM9 Based Platforms)

06/24/2019

GG 04:38 PM Software Development: RE: uPP receive clock lower limitation in SDR (Single Data Rate mode)

Hi Vivek,
I believe the datasheet is saying that regardless of whether the clock is being used as DDR or SDR the rate cannot be set below 4.69 MHz. However, this also seems to be assuming a default CPU clock of 300 MHz. This all see... Gregory Gluszek

06/21/2019

VP 08:05 AM Software Development: uPP receive clock lower limitation in SDR (Single Data Rate mode)

Hi,
I have a custom board with
-- MityDspl-138F module (with FPGA)
-- No Ethernet port
-- UART,USB,SD CARD interface
we have done following steps till date.
-- I have built VM with MityDSP Critical_Link_Unified_VM_14-04_04-2... Vivek Ponnani

06/06/2019

JC 03:12 PM Software Development: RE: MityDSPL138

VIDYA J wrote:
> But in CCS they are asking initialization file for the processor.
When your building? Jonathan Cormier

VJ 03:10 PM Software Development: RE: MityDSPL138

But in CCS they are asking initialization file for the processor. VIDYA J

JC 01:16 PM Software Development: RE: MityDSPL138

VIDYA J wrote:
> I used UART_echo code from OMAPL138_StarterWare_1_10_03_03 folder. For coding ARM i read like i need to add gel file. Can you provide me the corresponding gel file. Without gel file when i tried the code was not getting... Jonathan Cormier

VJ 06:13 AM Software Development: RE: MityDSPL138

I used UART_echo code from OMAPL138_StarterWare_1_10_03_03 folder. For coding ARM i read like i need to add gel file. Can you provide me the corresponding gel file. Without gel file when i tried the code was not getting debugged, but whi... VIDYA J