Project

General

Profile

Activity

From 12/09/2017 to 01/07/2018

01/04/2018

VP 02:06 PM Software Development: Real time signal input and output with uPP interface in MityDSP
Hi,
I have a custom board with
1) MityDspl-138F module (with FPGA)
2) No Ethernet port
3) UART,USB,SD CARD interface
4) We are using ADC5560 and DAC5672, reference is taken from Analog Expansion Board.
ADC and DAC both operates ...
Vivek Ponnani

12/27/2017

09:57 AM Software Development: RE: Changing UART1 to UART2 in Linux Kernel
Just noticed I left the @bootargs@ as @ttyS1@.
Changing that to @ttyS2@ solved that issue.
Sorry, I wasn't expecting such a simple solution.
Okan Çalış
05:32 AM Software Development: Changing UART1 to UART2 in Linux Kernel
Hi,
We've been working on a MityDsp-L138F board, and I can boot to Linux with NFS, with the following environment variables:
Okan Çalış

12/21/2017

VP 11:56 AM Software Development: Low frequency input (5 Hz to 20KHz processing) for mitydspl138F
Hi,
I have a custom board with
1) MityDspl-138F module (with FPGA)
2) No Ethernet port
3) UART,USB,SD CARD interface
4) We are using ADC5560 and DAC5672, reference is taken from Analog Expansion Board.
ADC and DAC both operat...
Vivek Ponnani

12/12/2017

JC 11:13 PM FPGA Development: RE: Core Creation Guidelines
Jorden Luke wrote:
> I am trying to get some help with this one as well. Is there are up date to this one?
It doesn't look like we ever created that guide. I'd recommend looking at the provided source files as examples.
examples/...
Jonathan Cormier
JL 06:52 PM FPGA Development: RE: Core Creation Guidelines
I am trying to get some help with this one as well. Is there are up date to this one? Jorden Luke

12/11/2017

JC 05:01 PM Software Development: RE: Loading kernel to SPI flash and Root file system .jffs2 to NAND.
Vivek Ponnani wrote:
> My queries are as below
> ...
Looks fine.
>
> ...
You'd want to extract the MDK filesystem, update the files and then generate the jffs2 image file. NOTE: We also generate a new tarball which we can archive o...
Jonathan Cormier
VP 02:24 PM Software Development: Loading kernel to SPI flash and Root file system .jffs2 to NAND.
Hi,
I have a custom board with
1) MityDspl-138F module (with FPGA)
2) No Ethernet port
3) UART,USB,SD CARD interface
we have done following steps till date.
1) I have built VM with MityDSP Critical_Link_Unified_VM_14-04_04-2...
Vivek Ponnani
 

Also available in: Atom