Activity
From 01/15/2017 to 02/13/2017
01/31/2017
- AB 06:48 PM PCB Development: RE: FPGA CLOCK LOCATION
- Alex,
Thank you for reaching out to us about this question.
On our MitySOM-L138F family modules we have the EMIF bus from the OMAP-L138 connected to the Xilinx Spartan 6 FPGA to allow for communications of cores between the process...
01/30/2017
- Hello good day I developing a new project in ISE WEBPACK using the PROFIBUS DEVELOPMENT KIT with the MitySOM-1810F Processor Card.
I am programming the FPGA and this is my entity:
PORT(
*CLK50* : IN STD_LOGIC;
RX : IN STD_LOG...
01/23/2017
- JA 10:59 AM Software Development: RE: Programming the FPGA - Loading via CPU
- Hello, good day
I load the FPGA with "Example loading the .bin file over the serial port using Kermit" because it was easier but I will continue trying with TFTP server.
U-Boot > loadb 0xC0700000
## Ready for binary (kermit) ... - MW 06:58 AM Software Development: RE: SATA link down
- Are you using SATA-II or SATA-III link speeds? I believe the Errata from TI still applies.
01/22/2017
- FX 10:37 PM Software Development: RE: SATA link down
- hello ,I have the same problem !
Can you tell me this problem is Finish or not?
01/20/2017
- JC 01:51 PM Software Development: RE: Programming the FPGA - Loading via CPU - "ERROR LOADING"
- Jesus Alejandro Alvarez Trejo wrote:
> Hello, Good Day
> ...
Your ping command was run while booted into linux. You should run it while in u-boot to prove you have network communication working.
>
> ...
What tftp server are you usi... - JA 12:51 PM Software Development: RE: Programming the FPGA - Loading via CPU - "ERROR LOADING"
- Hello, Good Day
I am trying to load the FPGA using https://support.criticallink.com/redmine/projects/arm9-platforms/wiki/Programming_the_FPGA vía CPU, I already created the .bin file to do the first test. I am using the ...