Mity CPU Platforms » MityDSP-L138 (ARM9 Based Platforms)

03/26/2015

JC 11:21 AM Software Development: RE: Pull-up Enable for MityDSP L138 (cp[0])

To be more specific, @CP[0]@ covers the following pins: @GP0[8] (OMAP_GP0_8), GP0[9] (OMAP_GP0_9), AHCLKX (AUDIO_SYSCLK), AHCLKR (AUDIO_SYSCLK), AFSX (AUDIO_FRAME), GP0[13] (OMAP_GP0_13), ACLKX (AUDIO_CLK), GP0[15] (OMAP_GP0_15)@
* T... Jonathan Cormier

03/25/2015

CB 10:57 AM FPGA Development: RE: Mity L138F FPGA -> OMAP interrupt lines

Hi Alex,
I was using MDK_2012-03-12 and in the included UCF the IO standard on those pin was different:
NET "o_nmi_n" LOC = "N8" | IOSTANDARD = LVCMOS33;
NET "o_int<0>" LOC = "K6" | IOSTANDARD = LVCMOS33;
NET "o_int<1>" LOC = "F2... Christopher Brunson

RK 10:55 AM Software Development: Pull-up Enable for MityDSP L138 (cp[0])

I'm trying to get a new hardware design up and running with the MityDSP L138, using the Industrial IO board as a starting point. I've noticed that in U-Boot, the enables set at DAVINCI_PUPD_ENA for groups 5, 8, 9 and 15 are set to 0 (di... Ronald Kabler

03/23/2015

AB 05:08 PM FPGA Development: RE: Mity L138F FPGA -> OMAP interrupt lines

Chris,
Hopefully you happened upon this on your own but the details for the pin-configuration, voltage standards, can be found in the sample .ucf files we provide in the MDK BSP (https://support.criticallink.com/redmine/projects/arm9-... Alexander Block

03/12/2015

AB 11:06 AM FPGA Development: RE: FPGA serial programming interface

We are happy to provide further assistance with this issue, however I will be contacting you directly at your e-mail address that is on-file.
Thank you.
Alex Alexander Block

03/11/2015

SB 10:23 AM FPGA Development: RE: FPGA serial programming interface

Thanks for the information.
We are prototyping a future product and due to pin count restrictions we can't use parallel slave mode.
How are the two resistors called, Rxxx and Ryyy ? stephan berner

AB 10:18 AM FPGA Development: RE: FPGA serial programming interface

I discussed this with one of our engineers here and it may be possible however they is likely a bit of work required in order to make it functional.
As well he wanted to know what the reasoning is behind programming the FPGA in the Sl... Alexander Block

AB 08:32 AM FPGA Development: RE: FPGA serial programming interface

SB,
I apologize.
The M0 and M1 FPGA pins are tied to resistors on the module to GND (M0) and 3.3V (M1) forcing the mode to Slave SelectMAP. The CCLK and DIN connections are tied to the OMAP-L138 processor.
It may be possible to... Alexander Block

03/10/2015

SB 05:04 PM FPGA Development: RE: FPGA serial programming interface

I understand that. However, I would like to configure the FPGA in serial slave mode. stephan berner

AB 05:01 PM FPGA Development: RE: FPGA serial programming interface

SB,
The FPGA is configured using 8 bit parallel slave select mode via the EMIFA bus connection to the Omap L138 processor.
Please reference this Wiki page for information about programming the FPGA: https://support.criticallink.co... Alexander Block

SB 03:36 PM FPGA Development: FPGA serial programming interface

hi,
are the pins CCLK, DIN and the MODE pins available on the OMAP-138 as GPIOs, or are they open/hardcoded on the PCB.
SB
stephan berner