Mity CPU Platforms » MityDSP-L138 (ARM9 Based Platforms)

03/12/2015

AB 11:06 AM FPGA Development: RE: FPGA serial programming interface

We are happy to provide further assistance with this issue, however I will be contacting you directly at your e-mail address that is on-file.
Thank you.
Alex Alexander Block

03/11/2015

SB 10:23 AM FPGA Development: RE: FPGA serial programming interface

Thanks for the information.
We are prototyping a future product and due to pin count restrictions we can't use parallel slave mode.
How are the two resistors called, Rxxx and Ryyy ? stephan berner

AB 10:18 AM FPGA Development: RE: FPGA serial programming interface

I discussed this with one of our engineers here and it may be possible however they is likely a bit of work required in order to make it functional.
As well he wanted to know what the reasoning is behind programming the FPGA in the Sl... Alexander Block

AB 08:32 AM FPGA Development: RE: FPGA serial programming interface

SB,
I apologize.
The M0 and M1 FPGA pins are tied to resistors on the module to GND (M0) and 3.3V (M1) forcing the mode to Slave SelectMAP. The CCLK and DIN connections are tied to the OMAP-L138 processor.
It may be possible to... Alexander Block

03/10/2015

SB 05:04 PM FPGA Development: RE: FPGA serial programming interface

I understand that. However, I would like to configure the FPGA in serial slave mode. stephan berner

AB 05:01 PM FPGA Development: RE: FPGA serial programming interface

SB,
The FPGA is configured using 8 bit parallel slave select mode via the EMIFA bus connection to the Omap L138 processor.
Please reference this Wiki page for information about programming the FPGA: https://support.criticallink.co... Alexander Block

SB 03:36 PM FPGA Development: FPGA serial programming interface

hi,
are the pins CCLK, DIN and the MODE pins available on the OMAP-138 as GPIOs, or are they open/hardcoded on the PCB.
SB
stephan berner

03/05/2015

FC 05:20 PM Software Development: RE: Write to SharedMem from DSP and read it from ARM

Thanks for the cache info. Completely missed that part.
I reverted to the original code, and I've added BCACHE_wb() call after I write to memory on the DSP side, but I still have a problem somewhere.
I changed the SHARED_MEM_BASE t... Frank C

02/19/2015

JC 10:48 AM Software Development: RE: MDK_2012-08-10 default configuration

There also may be a small time penalty in having the kernel search for the phy. But this would need to be quantified to really claim it as a problem. Jonathan Cormier

JC 10:46 AM Software Development: RE: MDK_2012-08-10 default configuration

I believe the phy address was set in an earlier version of the kernel and it was carried forward. There is also the case where the baseboard has a switch which identifies itself as multiple phy addresses and thus you would need to speci... Jonathan Cormier

FT 09:52 AM Software Development: RE: MDK_2012-08-10 default configuration

Thanks Mike for answer.
I did not look at section 2.2 of TLK100PHP datasheet. It is my fault.
I read section "3.3 PHY address" where it said
"Because all the PHYAD[4:0] pins have weak internal pull-down resistors,
the default s... François Tremblay

MW 09:18 AM Software Development: RE: MDK_2012-08-10 default configuration

Hi François,
In the datasheet for the TLK100PHP, Section 2.2 shows that the PHYAD0 pin has an internal pull-up, which is why it is reading a '1' (there are no pullups on the DevKit card, and we are tri-stating the MII_COL and RXD0-RXD... Michael Williamson

FT 07:33 AM Software Development: RE: MDK_2012-08-10 default configuration

I look at U-boot code and it doesn't explain what we are seeing.
When resetting the PHY device, only GPIO5[15] is activated with pin mux. Other pins are left 3-stated.
Look at line 113 of board/davinci/mityomapl138/mityomapl138.c. Al... François Tremblay