Activity
From 02/13/2015 to 03/14/2015
03/12/2015
- AB 11:06 AM FPGA Development: RE: FPGA serial programming interface
- We are happy to provide further assistance with this issue, however I will be contacting you directly at your e-mail address that is on-file.
Thank you.
Alex
03/11/2015
- SB 10:23 AM FPGA Development: RE: FPGA serial programming interface
- Thanks for the information.
We are prototyping a future product and due to pin count restrictions we can't use parallel slave mode.
How are the two resistors called, Rxxx and Ryyy ? - AB 10:18 AM FPGA Development: RE: FPGA serial programming interface
- I discussed this with one of our engineers here and it may be possible however they is likely a bit of work required in order to make it functional.
As well he wanted to know what the reasoning is behind programming the FPGA in the Sl... - AB 08:32 AM FPGA Development: RE: FPGA serial programming interface
- SB,
I apologize.
The M0 and M1 FPGA pins are tied to resistors on the module to GND (M0) and 3.3V (M1) forcing the mode to Slave SelectMAP. The CCLK and DIN connections are tied to the OMAP-L138 processor.
It may be possible to...
03/10/2015
- SB 05:04 PM FPGA Development: RE: FPGA serial programming interface
- I understand that. However, I would like to configure the FPGA in serial slave mode.
- AB 05:01 PM FPGA Development: RE: FPGA serial programming interface
- SB,
The FPGA is configured using 8 bit parallel slave select mode via the EMIFA bus connection to the Omap L138 processor.
Please reference this Wiki page for information about programming the FPGA: https://support.criticallink.co... - hi,
are the pins CCLK, DIN and the MODE pins available on the OMAP-138 as GPIOs, or are they open/hardcoded on the PCB.
SB
03/05/2015
- FC 05:20 PM Software Development: RE: Write to SharedMem from DSP and read it from ARM
- Thanks for the cache info. Completely missed that part.
I reverted to the original code, and I've added BCACHE_wb() call after I write to memory on the DSP side, but I still have a problem somewhere.
I changed the SHARED_MEM_BASE t...
02/19/2015
- JC 10:48 AM Software Development: RE: MDK_2012-08-10 default configuration
- There also may be a small time penalty in having the kernel search for the phy. But this would need to be quantified to really claim it as a problem.
- JC 10:46 AM Software Development: RE: MDK_2012-08-10 default configuration
- I believe the phy address was set in an earlier version of the kernel and it was carried forward. There is also the case where the baseboard has a switch which identifies itself as multiple phy addresses and thus you would need to speci...
- FT 09:52 AM Software Development: RE: MDK_2012-08-10 default configuration
- Thanks Mike for answer.
I did not look at section 2.2 of TLK100PHP datasheet. It is my fault.
I read section "3.3 PHY address" where it said
"Because all the PHYAD[4:0] pins have weak internal pull-down resistors,
the default s... - MW 09:18 AM Software Development: RE: MDK_2012-08-10 default configuration
- Hi François,
In the datasheet for the TLK100PHP, Section 2.2 shows that the PHYAD0 pin has an internal pull-up, which is why it is reading a '1' (there are no pullups on the DevKit card, and we are tri-stating the MII_COL and RXD0-RXD... - FT 07:33 AM Software Development: RE: MDK_2012-08-10 default configuration
- I look at U-boot code and it doesn't explain what we are seeing.
When resetting the PHY device, only GPIO5[15] is activated with pin mux. Other pins are left 3-stated.
Look at line 113 of board/davinci/mityomapl138/mityomapl138.c. Al...
02/18/2015
- FT 04:59 PM Software Development: RE: MDK_2012-08-10 default configuration
- Thanks Jonathan to told me that I am not alone with that questioning.
The first revision of our custom board had a mistake and PHYAD4 what pulled-up instead of PHYAD1.
The PHYAD0 is not pulled is any direction (as on Industrial board... - JC 04:43 PM Software Development: RE: MDK_2012-08-10 default configuration
- François,
I too was confused about this but was unable to determine why the phy id becomes 0x03.
I checked the SoM schematic and the MII_COL pin is directly connected to the SoC with no pull ups.
U-boot specifically disables p... - FT 04:21 PM Software Development: RE: MDK_2012-08-10 default configuration
- Mike,
My reply is out of date but it is about that topic: PHY address configuration.
You said that PHY address is set to 0x03 on Industrial board.
When I look at 0-000268RI schematic, only PHYAD1 pin is pulled up. There is no p... - JC 03:59 PM Software Development: RE: Write to SharedMem from DSP and read it from ARM
- Pretty sure you have to flush the DSP cache after changing values.
- FC 03:48 PM Software Development: RE: Write to SharedMem from DSP and read it from ARM
- Hi,
I am trying to get the shared memory working as well (by writing from DSP side and reading back from ARM side) using the HelloWorld as a basis. But ARM side doesn't read back correct values. I am using the same stuff from here. It...
02/17/2015
- MA 11:41 AM Software Development: RE: Alter Ethernet MAC
- Thanks Jonathan, that's exactly what I was after.
- MW 11:41 AM Software Development: RE: Alter Ethernet MAC
- You might also try this technique, though I am not sure if the current version of the 3.2 kernel has this command line option implemented:
http://developer.ridgerun.com/wiki/index.php/How_to_pass_ethernet_address_to_linux_kernel_ether... - JC 11:26 AM Software Development: RE: Alter Ethernet MAC
- Mostafa,
We store the mac address on a eeprom on the SoM. The settings stored on this can be accessed using the factoryconfig command in U-boot. Beware that you can brick the SOM if you change some of the other fields. - Hi, is it possible to alter the 'burned-in' MAC address of an L138F? I know that I can change it using 'ifconfig eth0 hw ether XX:XX:XX:XX:XX:XX' once Linux is up and running but was wondering if it's possible to make this change persist...