Activity

From 10/26/2014 to 11/24/2014

CC 09:23 AM Software Development: RE: inotify issue: This is a non-problem. It is working fine. Sorry for the trouble. Chris Coonan
JC 09:12 AM Software Development: RE: inotify issue: Could you provide some example code that shows the problem you are having? Also need a better explanation of what problem you are seeing.
I am not aware of anyone here who has tried using inotify on the L138, so providing us with a ... Jonathan Cormier
CC 07:31 AM Software Development: RE: inotify issue: My mistake. Cut and paste error. The kernel is 2.6.34-RC1.
Chris Coonan

CC 12:09 PM Software Development: inotify issue: Trying to get inotify to execute properly from inside my application code. I am using linux kernel 2.24-RC1.
Are there any known issues with this, or do I have a configuration problem? Any help greatly appreciated.
Thanks,
Chris... Chris Coonan

GG 05:16 PM Software Development: RE: FPGA configuration via u-Boot problem: You can also use the promgen command to generate a bin file from a bit:
promgen -w -p bin -u 0 filename.bit -o filename.bin
\Greg Gregory Gluszek
MW 07:29 AM FPGA Development: RE: PlanAhead issue: For ISE (and I think ISE / PlanAhead are still the tools for Spartan 6, as the Vivado tools are for 7 series and higher), if you analyze your design with commercial temp and keep the non-commercial parts within their rated voltages and t... Michael Williamson
OM 03:21 AM FPGA Development: PlanAhead issue: Hi,
Why at creation of the project in PlanAhead 14.7 for the chip xc6slx45csg324-3 it is not possible to specify Temp Grade I (only C)? In fact according to the specification on L138-FI-236-RL-ND it works in a range-40°C ~ 70°C.
Best... Oleh Mela

SK 07:51 AM Software Development: RE: FPGA configuration via u-Boot problem: Hey,
I solved the problem.
It's important that the FPGA config file <fpga>.bin file was created correctly.
By using Xilinx Impact I selected the following options in the "Create PROM file" dialog:
1. Generic Parallel PROM
2. ... Stefan Krassin
SK 07:30 AM Software Development: FPGA configuration via u-Boot problem: Hi all,
I have a problem with the configuration of the FPGA and booting linux.
I followed the instructions from CL "Using u-Boot to load the FPGA".
If I run the boot command "bootcmd=sf probe 0; sf read 0xc0700000 0x100000 0x280... Stefan Krassin

DG 01:52 PM Software Development: RE: Real time SATA writes: Hi Mary,
As you suspected in your original post, it is likely that when you are calling fwrite, in some cases the write cache is full and is causing full flush down to storage (NAND). In this case it will take longer than just writing... Dominic Giambo
MF 01:04 PM Software Development: RE: Real time SATA writes: After further testing and setting optimization, I have narrowed down the delay:
The call to fwrite() normally takes about 2.5 msec, but occasionally (on the order of minutes) this call can take 20 msec, 40 msec, 150 msec, or even 300... Mary Frantz

OM 10:44 AM FPGA Development: Clock for FPGA: Hi.
I'm using MityDSP-L138F Board. As will ensure that the generated clock signal to FPGA?
Thanks Oleh Mela

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Mity CPU Platforms » MityDSP-L138 (ARM9 Based Platforms)