Activity
From 10/19/2014 to 11/17/2014
11/17/2014
- GG 05:16 PM Software Development: RE: FPGA configuration via u-Boot problem
- You can also use the promgen command to generate a bin file from a bit:
promgen -w -p bin -u 0 filename.bit -o filename.bin
\Greg - MW 07:29 AM FPGA Development: RE: PlanAhead issue
- For ISE (and I think ISE / PlanAhead are still the tools for Spartan 6, as the Vivado tools are for 7 series and higher), if you analyze your design with commercial temp and keep the non-commercial parts within their rated voltages and t...
- Hi,
Why at creation of the project in PlanAhead 14.7 for the chip xc6slx45csg324-3 it is not possible to specify Temp Grade I (only C)? In fact according to the specification on L138-FI-236-RL-ND it works in a range-40°C ~ 70°C.
Best...
11/14/2014
- SK 07:51 AM Software Development: RE: FPGA configuration via u-Boot problem
- Hey,
I solved the problem.
It's important that the FPGA config file <fpga>.bin file was created correctly.
By using Xilinx Impact I selected the following options in the "Create PROM file" dialog:
1. Generic Parallel PROM
2. ... - Hi all,
I have a problem with the configuration of the FPGA and booting linux.
I followed the instructions from CL "Using u-Boot to load the FPGA".
If I run the boot command "bootcmd=sf probe 0; sf read 0xc0700000 0x100000 0x280...
11/10/2014
- DG 01:52 PM Software Development: RE: Real time SATA writes
- Hi Mary,
As you suspected in your original post, it is likely that when you are calling fwrite, in some cases the write cache is full and is causing full flush down to storage (NAND). In this case it will take longer than just writing... - MF 01:04 PM Software Development: RE: Real time SATA writes
- After further testing and setting optimization, I have narrowed down the delay:
The call to fwrite() normally takes about 2.5 msec, but occasionally (on the order of minutes) this call can take 20 msec, 40 msec, 150 msec, or even 300...
10/31/2014
- Hi.
I'm using MityDSP-L138F Board. As will ensure that the generated clock signal to FPGA?
Thanks
10/24/2014
- MW 10:41 AM PCB Development: RE: L138 SOM LEDs
- Sorry,
On Non-FPGA modules:
D1 is connected to R16 (GP6_12) of the OMAP-L138.
D2 is connected to R17 (GP6_13) of the OMAP-L138.
-Mike
- AK 10:05 AM PCB Development: RE: L138 SOM LEDs
- Hi Mike,
The SOM we are using is the non-FPGA version. What do D1 and D2 connect to?
Thanks,
Anton - MW 07:22 AM PCB Development: RE: L138 SOM LEDs
- D1 is connected to the FPGA_DONE pin on the FPGA configuration block.
D2 is connected to P15 of the FPGA IO_L74P_AWAKE_1
D3 is connected to P16 of the FPGA IO_L74N_DOUT_BUSY_1
-Mike
- AK 10:03 AM PCB Development: RE: MityDSP-L138 Boot Problem
- This issue has been resolved - we had left an uterminated SPI1_CLK signal trace on our base board at an unpopulated device.
Anton
10/22/2014
- Please can you provide information for D1 and D2 LEDs on the L138-FX-225-RC module. What are they connected to?
Thanks,
Anton - We are using the L138-FX-225-RC on a new custom baseboard and are having trouble with boot:
- no UART activity in normal SPI boot
- UART boot mode sends "BOOTME"
We attempted to erase and flash the bootloader using the WinCE boot pa...