Activity
From 05/14/2014 to 06/12/2014
06/06/2014
- UF 06:36 PM Software Development: RE: DSP HelloWorld
- Flashing the 2014 MDK files solved all the problems. For some reason installing the U-boot bricked my board, but following the wiki on "reprogramming a dead board" fixed it.
I have another question. Is there a sample Makefile for buil... - JC 08:37 AM Software Development: RE: DSP HelloWorld
- The filesystem and kernel that ship preprogrammed on the L138 is quite old. You should have more luck if you flash the u-boot, kernel, and filesystem included in the 2014-01-13 MDK.
Installing U-boot:
https://support.criticallink.co... - BD 10:02 AM Software Development: RE: Login uncorrect from serial connection and correct from ethernet connetion
- Silvano, as a test, you can rename the securetty file which should eliminate any restrictions on root logins.
- JC 09:51 AM Software Development: RE: Login uncorrect from serial connection and correct from ethernet connetion
- My securetty file has following at the top of the file which i didn't see in the file you posted.
- JC 09:49 AM Software Development: RE: Login uncorrect from serial connection and correct from ethernet connetion
- I updated to the latest filesystem and got similar results to my previous post.
- JC 08:54 AM Software Development: RE: Login uncorrect from serial connection and correct from ethernet connetion
- Testing this on a L138 at my desk. I am able to login as root over ssh using any password including an empty password. But am having no trouble logging in over the serial port.
After setting a password I can no longer login using ... - SB 08:47 AM Software Development: RE: Login uncorrect from serial connection and correct from ethernet connetion
- Is there something wrong?
Any idea? - SB 08:19 AM Software Development: RE: Login uncorrect from serial connection and correct from ethernet connetion
- Attached you can find:
- a startup screenshot;
- the content of /etc/ folder;
- the file securetty.
Let me know, thanks.
Silvano - SB 08:01 AM Software Development: RE: Login uncorrect from serial connection and correct from ethernet connetion
- From serial I do the access without password but when I write "root" at login it tells me "login incorrect".
From ethernet cable I do the access with "root" and password "mitydsp" but I do not set anything. - TI 08:00 AM Software Development: RE: Login uncorrect from serial connection and correct from ethernet connetion
- Normally, this is not a problem. can you check if there is an /etc/securetty file ( http://www.faqs.org/docs/securing/chap5sec41.html )
or log in over the network and then try to log in from the serial console and check the log files in... - MW 07:58 AM Software Development: RE: Login uncorrect from serial connection and correct from ethernet connetion
- Did you set a password for the root shell? Normally there is no password by default. How did you set the password?
-Mike
- SB 07:57 AM Software Development: RE: Login uncorrect from serial connection and correct from ethernet connetion
- Does anybady has any suggestion?
It is important for me, not only to have the access from ethernet, but also from serial cable...
06/05/2014
- I'm trying to setup a development environment for the MityDSP-L138 to write DSP code.
I got the DSP HelloWorld test to work, but with a few blocking issues:
1. I had to use the HelloWorld program downloaded from the website. My own... - Dear all,
I have a strange problem.
I hava my MityDSP connected to my pc through both a serial cable and a ethernet cable.
The MityDSP works good. I installed the kernel on the SPI-FLASH and the file system in .jffs2 format on the... - SB 06:24 AM Software Development: RE: Kernel loading module problems MityDSP and FPGA configuration
- I have corrected all the CRC error rounding the filesize parameters to the correct values.
I have also recompiled the kernel modifyind a little our configuration baseboard-industrialio.c file beacuse we noticed that there was one error ...
06/04/2014
- MW 08:57 AM Software Development: RE: Kernel loading module problems MityDSP and FPGA configuration
- The filessize should be rounded to 0x800 bytes, which I think should be 0x150C800, not 0x150E000.
-Mike
- SB 08:49 AM Software Development: RE: Kernel loading module problems MityDSP and FPGA configuration
- Dear all
As I got a lot of CRC errors, here are some question:
1 My .jffs2 file is about 21 MB (22070432 bytes) which corresponds to 0x150C4A0. To copy the filesystem on the target I use the following commands, right?
u-Boot> mw.b 0...
06/03/2014
- SB 08:48 AM Software Development: RE: Kernel loading module problems MityDSP and FPGA configuration
- Dear Michael,
I tried to run the command you told me. Everything was ok until I copied the fpga_ctrl file on the target machine as you can see in the attached file fpga_ctrl_ontarget.png.
But when I run the "insmod" command I got wha...
06/01/2014
- AS 11:49 AM Software Development: RE: How to run bin application via u-boot?
- > If I knew the answer to using a bin file beyond "go", as you asked before, I would have told you before. :^)
I'm Sorry for my insistence.
> ...
No, the size didn't change much (debug out size is 3.06 MB and release out size is 2.8... - MW 10:19 AM Software Development: RE: How to run bin application via u-boot?
- Hi Ahmed,
If I knew the answer to using a bin file beyond "go", as you asked before, I would have told you before. :^)
So you set the --symdebug:none option and the filesystem grew on your Release build from 2MB to 3MB? That's odd... - AS 04:39 AM Software Development: RE: How to run bin application via u-boot?
- Hi Mike,
I have set the compiler option to "--symdebug:none" and the size of the .out file generated is also 3 MB.
Is there another option to minimize the size of out file? and as i asked you before is there a Uboot command to execute ...
05/30/2014
- MW 11:02 AM Software Development: RE: Kernel loading module problems MityDSP and FPGA configuration
- Did you also rebuild the FPGA drivers? They are not in-tree in the kernel git repository. They are located in the board support package in the MityDSP Developer's Kit.
Let's start with this:
On the build machine: - SB 10:40 AM Software Development: RE: Kernel loading module problems MityDSP and FPGA configuration
- Dear Michael,
let me know if my way of working is right:
1) I wrote my own baseboard-industrialio.c file as reported in the firts post of this discussion.
2) I recompiled the kernel as reported in https://support.criticallink.com/re... - MW 07:30 AM Software Development: RE: Kernel loading module problems MityDSP and FPGA configuration
- Hello,
We have many customers able to load and run modules with the MityDSP-L138, it's not obvious what the issue is here. I am suspicious that there may have been a problem with the filesystem installation / update (either the modul... - SB 04:00 AM Software Development: RE: Kernel loading module problems MityDSP and FPGA configuration
- Dear all,
attached you can find a text (LinuxLoading.txt) file where I captured the entire boot together with the screenshot where "Failed" occurs (FailuresLoadingKernel.png).
I also run "uname -a" and the results are in the text fil... - AS 03:45 AM Software Development: RE: How to run bin application via u-boot?
- Michael Williamson wrote:
> Just to confirm, you have the compiler option "--symdebug:none" in your release compile and link options?
> ...
Thanks Mike.
Unfortunately I didn't check this compiler option and now It's my weekend so I'll...
05/29/2014
- AB 04:29 PM Software Development: RE: How to run bin application via u-boot?
- Ahmed,
I believe Mike was suggesting that you build the application as a "release" version without any debugging and see what the resulting application file size is?
I.E. if it was 5MB in debug maybe it's 2MB in release, thus no ne... - MW 04:04 PM Software Development: RE: How to run bin application via u-boot?
- Just to confirm, you have the compiler option "--symdebug:none" in your release compile and link options?
-Mike
- AS 03:51 PM Software Development: RE: How to run bin application via u-boot?
- Hi Mike,
I have tried what you mentioned and it didn't work.
I'll wait your trial.
Thanks in advance. - MW 03:02 PM Software Development: RE: How to run bin application via u-boot?
- I think you need to strip the .out file (make a release version that removes the debugging information).
If I get a second I will try it out.
-Mike
- AB 01:48 PM Software Development: RE: How to run bin application via u-boot?
- Posting some previous direct followup e-mails from the customer.
I have followed the steps of the Starterware wiki ([[https://support.criticallink.com/redmine/projects/arm9-platforms/wiki/StarterWare]]) and I could run elf (UART_MITY_... - MW 10:47 AM Software Development: RE: Kernel loading module problems MityDSP and FPGA configuration
- Hi,
Can you please capture the entire boot up on the console to a text file and set it over?
Or at least run "uname -a" and report the results?
-Mike
- SB 10:38 AM Software Development: RE: Kernel loading module problems MityDSP and FPGA configuration
- Dear Bob,
when I try to load the modules with "insmod fpga_ctrl.ko" I get an error with "Function non implemented" as explanation.
I also found on internet that the insmod error message is caused by either a kernel lacking module sup... - BD 09:30 AM Software Development: RE: Kernel loading module problems MityDSP and FPGA configuration
- Hi Silvano,
Jon was referring to the kernel modules explicitly. The modules need to be installed in your target root filesystem (/lib/$kernelversion) after you copy over the kernel.
The page you reviewed, does mention this, but it'... - SB 08:47 AM Software Development: RE: Kernel loading module problems MityDSP and FPGA configuration
- I report before that I recompile the kernel every time I made a modificatuon on the baseboard file.
In fact the link you report me is cited by me in my first message.
Maybe there is something wrong in the file or in the compiling.
Cou... - JC 08:24 AM Software Development: RE: Kernel loading module problems MityDSP and FPGA configuration
- Its hard to tell from those error messages whats going on but have you tried recompiling the kernel modules when you made changes to the kernel?
See https://support.criticallink.com/redmine/projects/arm9-platforms/wiki/FPGA_Core_Devic... - Hello everybody.
I am Silvano Bertoldo, I mainly work on the software side of MityDSP and I have a big problem about the linux kernel I am not able to solve. I am very grateful if you can support me or forward the present email to a s... - JC 09:53 AM Software Development: RE: Compiler does not run in VM
- Also our vm does come with the toolchain installed. I'm unsure why you were unable to locate it.
Try looking in /usr/local/oecore-i686
The instructions seem to be missing that you need to run @. /usr/local/oecore-i686/environment-s... - MW 09:29 AM Software Development: RE: Compiler does not run in VM
- Yes. You need to run the 32-bit version in the VM if your VM is a 32-bit architecture.
on your VM type "uname -a". It should tell you the version of the VM architecture.
-Mike - Hello- I'm new to the MityDSP platform and I am having trouble getting the development environment working. I have imported the VM into VirtualBox, and can run the VM. I'm trying to get the environment going for the L138F (ARM9). I fo...
05/28/2014
- Hi everyone,i have MityARM1808F.
I could use "bootelf" command[ex: bootelf 0xc0700000] to run any app.out,but the size of .out format is usually large(in my case is about 5 Mega byte which is too large to be saved on SPI flash with FPGA... - AS 08:54 AM Software Development: RE: UPP ISR is not called
- Finally i could solve this issue by adding the following code :
asm(" mrc p15, #0, r0, c1, c0, #0\n\t"
" orr r0, r0, #0x00002000\n\t"
" mcr p15, #0, r0, c1, c0, #0\n\t");
before calling BIOS_start function.
...
05/19/2014
- AS 04:43 PM FPGA Development: RE: Programming FPGA Flash using IMPACT
- Thanks Michael,
I shall follow the steps in the link you mentioned and let you know results.
05/17/2014
- RK 12:45 PM Software Development: RE: DSP- EDMA Transmission problem
- Hello again,
I am now trying to transmit data using upp interface. On the FPGA- side the interface works correctly, but on the DSP- side I cannot receive data, that is, My message queue wouldn't wake. I did the following in my DSP/BIOS ...
05/16/2014
- MW 05:55 PM Software Development: RE: EMIF Clock in U-Boot
- Hello,
I assume you mean the EMIFA clock (to FPGA) not the EMIF clock (used for the DDR).
I am sorry I missed this. I believe the EMIF clock gets initialized in the User Boot Loader (the UBL), a copy of which is included in the bo...
05/15/2014
- MW 08:36 PM FPGA Development: RE: Programming FPGA Flash using IMPACT
- Hi,
Please take a look at the [[Programming the FPGA]] wiki page for information about programming the FPGA.
The FPGA can be programmed via JTAG or via 8 bit parallel slave select mode through the OMAP-L138 (or AM18XX) EMIFA databu...
05/14/2014
- Hi everyone,
I'am using CCS V5.3 and emulator XDS100V2.
I have developed SYS/BIOS ARM app. which use UPP to send/receive data to/from FGPA. Everything works fine(an interrupt is received when data has been sent/received to/from FP...