Activity
From 02/15/2014 to 03/16/2014
03/11/2014
- RK 05:13 PM Software Development: RE: DSP- EDMA Transmission problem
- Hello Mike,
Thank you very much for your response.
I have a question before I transfer to other place than L2 Cache. I found in the forum the information about the usage of memory:
https://support.criticallink.com/redmine/projects/...
03/10/2014
- MW 07:25 AM Software Development: RE: DSP- EDMA Transmission problem
- Do you see this affect if you transfer to a different place in DDR (instead of the L2 SRAM)?
Are you still enabling the DSP L2 Cache? You can't enable L2 Cache and also try to use it directly as shared RAM unless you reduce the cac... - RK 07:19 AM Software Development: RE: DSP- EDMA Transmission problem
- Hello Michael,
It looks like edma is causing that. When I turned the edma off and used the data without transferring it to L2_Cache. That is, I am attempting to transfer the data block from 0x66000880 to L2_Cache in 0x11820000 for perfo...
03/09/2014
- MW 03:44 PM Software Development: RE: DSP- EDMA Transmission problem
- It sort of sounds like there is a memory leak somewhere. Are you thinking it's in the DspQDMA routines?
-Mike - RK 03:29 PM Software Development: RE: DSP- EDMA Transmission problem
- Hello again,
There is another symptom in my application that occurs. I am viewing the size of heap in the MEM in the RTOS object view (ROV).The size of free memory in heap is drastically low just after the EDMA transfer is finished (and...
03/07/2014
- JP 09:13 AM Software Development: RE: "Breaking into" uboot
- Hello,
Thank you very much for your replies. I tried a different cable and it worked.
I attempted to update Linux filesystem by sshing in, changing the opkg feeds to an up to date repository and running opkg update. I see now that t... - BD 09:11 AM Software Development: RE: "Breaking into" uboot
- Hello Jordi,
Can you confirm that the serial cable provided with the dev kit has the words "Null Modem" printed on each connector?
-Bob
- JC 08:14 AM Software Development: RE: "Breaking into" uboot
- Also to ask the simple questions, have you tried with and without the null modem? I've run into serial cables that already did the null modem part so the adapter was not necessary.
- JC 08:13 AM Software Development: RE: "Breaking into" uboot
- JC 08:07 AM Software Development: RE: "Breaking into" uboot
- You should see printout similar to this:
- Hello, I have a MityDSP L138 and I am trying to gain access to u-boot. I have a NULL modem serial cable which was supplied with the MityDSP kit connected to my pc. The other end is connected to the adapter which was also supplied with th...
03/04/2014
- MF 09:11 AM Software Development: RE: How to add ifplugd to Busybox
-
> When you remove and reconnect the ethernet cable do you get any messages printed on the console?
> ...
No messages appear on the console.
> What version of the kernel are you running (custom or from which Critical Link MDK)?...
03/03/2014
- BD 01:05 PM Software Development: RE: How to add ifplugd to Busybox
- Mary,
Based upon a quick review, your method looks OK.
When you remove and reconnect the ethernet cable do you get any messages printed on the console?
What version of the kernel are you running (custom or from which Critical Li... - MF 09:46 AM Software Development: RE: How to add ifplugd to Busybox
- Sorry,... I hit enter before I was done above. Attached are the other script files
To build busybox, I first ran make with nothing enabled (step 2a above), then with menu_config.
I tried starting the ifplugd deamon from the comman... - MF 09:29 AM Software Development: RE: How to add ifplugd to Busybox
- I have done the following:
- ES 09:28 AM Software Development: RE: I2C Bus
- Thank you for your comments.
The glitches you can see on the waveforms occur when there is an acknowledge bit. The master stops driving and the slave starts. If they occurred on the clock line or during the high period of the clock I ...
03/02/2014
- RK 03:11 PM Software Development: RE: DSP- EDMA Transmission problem
- Hello,
Thank you for response. It is highly possible that the DMA transfer is triggered before the previous has not finished its transmission, but I don't know how to check it.I don't know how to check while debugging, whether or not th...
02/28/2014
- BD 11:01 AM Software Development: RE: How to add ifplugd to Busybox
- Mary,
In regards to question (2) either approach should work. If you want to replace busy box you will need to do that with a filesystem that is not in use. If you're using a MMC card you can copy over the replacement from a another ... - I want to add ifplugd to Busybox so that the system can detect ethernet cable plug/unplug events and reinitialize the network when the cable is plugged in.
I read this page:
https://support.criticallink.com/redmine/projects/arm9-plat...
02/27/2014
- MW 07:42 AM Software Development: RE: I2C Bus
- I don't like the glitches in your "noramal operation" or "early termination" scope plots. Those should not be there.
I am looking at the datasheets for the MCP3426 and the DS1682.
Both appear to have the potential for the I2C slav... - ES 05:21 AM Software Development: RE: I2C Bus
- Any comments on the waveforms I posted?
Ed Smith
02/26/2014
- JC 09:35 AM Software Development: RE: MityDSP-L138F SoM initial flash configuration
- Francois,
Every module is run through our test fixture which programs the bootloader into NOR before running its tests.
Jonathan - Hi,
When a customer order MityDSP-L138F SoM from either your offcial distributors or directly from Critical Link,
are TI bootloader and U-Boot ALWAYS flashed into NOR flash memory?
I am asking this question because we have a proj...
02/25/2014
- ES 07:34 AM Software Development: RE: I2C Bus
- Thanks for the swift response. That is exactly the info I've been looking for.
I have attached some waveforms. The first is normal operation. The second shows the bus hanging at the end of the access. The third shows the master termin... - MW 06:59 AM Software Development: RE: I2C Bus
- The PMIC is TPS65023RSBT. The PROM is 24AA02-I/MS. Pins 1, 2, and 3, of the PROM are no-connects.
The I2C0_SCL and I2C0_SDA lines each have pullups (4.7K) to +3.3V.
Do you have scope traces of the I2C lines when this condition oc... - ES 06:24 AM Software Development: RE: I2C Bus
- I'm working with Bruce on this issue. It would be really helpful to have the part numbers of the other devices, particularly the PROM, and a schematic of the I2C portion of the circuit on the module.
Thanks
Ed Smith - MW 07:02 AM Software Development: RE: DSP- EDMA Transmission problem
- Is the first DMA completing before calling the second?
- RK 05:04 AM Software Development: RE: DSP- EDMA Transmission problem
- Hello again,
It appears that now the different problem occurs. When the DMA transmission is invoked twice or thrice, the DSP/BIOS goes to UTL_halt() state and in the ROV log is a message that there was an Opcode exception- Resource...
02/24/2014
- DR 07:38 AM Software Development: RE: DSP- EDMA Transmission problem
- Excellent! Glad it is now working!
Dave
- RK 07:15 AM Software Development: RE: DSP- EDMA Transmission problem
- Hello David,
Sorry for the latency-I corrected the code due to your suggestions and it worked- thank you.
Best Regards
02/23/2014
- Hej hej,
I would like to change the EMIF-Clock from 100 MHz to 25 MHz for a MityDSP L138-Module. I searched the u-boot-files but could not find the code where the pll dividers are set. In which file do I have to look?
Am I right, t...
02/19/2014
- MP 08:15 AM Software Development: RE: Why is MityDSP-L138F UPP transmit sometimes giving UOR events
- We leave it at 300 Mhz
- MW 08:08 AM Software Development: RE: Why is MityDSP-L138F UPP transmit sometimes giving UOR events
- When you boot linux, are you changing the CPU OPP to 456 MHz or leaving it at 300 MHz?
- MP 08:03 AM Software Development: RE: Why is MityDSP-L138F UPP transmit sometimes giving UOR events
- Hello,
Yes we have adjusted the bus master priority of uPP, but did not see any great improvements (strangely).
We have tried to set the uPP clock div to 1 (so 37.5 MHz) and the errors were flying. - MW 07:42 AM Software Development: RE: Why is MityDSP-L138F UPP transmit sometimes giving UOR events
- Did you check / adjust your UPP Bus master priorities?
- MP 07:33 AM Software Development: RE: Why is MityDSP-L138F UPP transmit sometimes giving UOR events
- Hello,
Just a quick update. When we do not boot into linux (just uboot) we do not see
these errors.
So booting linux has somehow influence on the uPP performence.
Again thanks for any assistants in this matter
02/18/2014
- GG 08:50 AM Software Development: RE: Why is MityDSP-L138F UPP transmit sometimes giving UOR events
- Hi Marc,
Here are a couple of other things to consider:
# In the past we've had throughput problems with TI's uPP drivers. That was a couple years ago, so maybe the drivers are improved or will work fine for your scenario. However... - MW 08:22 AM Software Development: RE: Why is MityDSP-L138F UPP transmit sometimes giving UOR events
- You might raise the priority up a bit (try 0 or 1). If the transfers are small, then it should be OK to give it priority.
-Mike
- MP 08:04 AM Software Development: RE: Why is MityDSP-L138F UPP transmit sometimes giving UOR events
- Hello,
Here are some answers to the questions:
* Are you trying to run continuous transfers?
- We do not run continuous but every 200 us (5 kHz)
* Do you get the error on every transmit, or periodically?
- No not every... - MW 07:17 AM Software Development: RE: Why is MityDSP-L138F UPP transmit sometimes giving UOR events
- Hi Marc,
Are you trying to run continuous transfers?
At 75 Mhz, you should be running a buffer rep rate of 64 / 75 MHz = 850 ns.
If you are trying to run continuous transfers, that would imply an interrupt rep-rate that fast.
... - MP 02:55 AM Software Development: RE: Why is MityDSP-L138F UPP transmit sometimes giving UOR events
- Hello,
Here are some answers to the questions:
* Are you using the Critical Link MDK drivers? If so, what version of the MDK are you using?
- We use TI's legacy uPP driver
- MDK_2013-05-15
* What is the CPU speed set t... - MW 07:22 AM Software Development: RE: I2C Bus
- Hi Bruce,
I believe that the I2C addresses for I2C0 are described in the "Carrier Board Design Guide":http://www.criticallink.com/wp-content/uploads/2014/01/MityDSP-L138-Carrier-Board-Design-Guide.pdf.
From section 3.3.8:
_All m... - We are currently investigating a problem accessing the I2C0 bus.
My initial enquiry is to find out what devices are on the MityDSP SOM to insure we are not conflicting.
Our SOM is a L138-DX-225-RI. We are using uBoot to boot t...
02/17/2014
- GG 09:25 AM Software Development: RE: Why is MityDSP-L138F UPP transmit sometimes giving UOR events
- Hi Marc,
If you are following the uPP design guidelines, then perhaps this is a true underflow or overflow condition. I have a number of questions about your project that can hopefully help us narrow down what the cause might be:
... - Hello,
We use the MityDSP-L138F and between DSP and FPGA we use UPP communication but transmit (channel A) is giving sometimes an UOR events.
What could be the cause of this error, we use the recommended clock source (PLL0_SYSCLK2) s...