Activity
From 09/29/2013 to 10/28/2013
10/25/2013
- SH 06:15 PM Software Development: RE: Can't get DMA using low level driver working on DSP
- Thanks for the replies. I'm using the 0x66000000 (CS5) space.
However, I was wrong about the interpretation of the hi-res clock in DSP/BIOS - each count is one CPU clock cycle, so the transfer rate is closer to 170ns per 16-bit word. ... - DR 08:46 AM Software Development: RE: Can't get DMA using low level driver working on DSP
- If you have cache enabled for the DDR, I don't think it should be much faster to use IRAM. Your DMA in this case will complete when the data is in cache, not when it is in DDR.
Transfers from the EMIF interface are not very efficient... - MW 07:45 AM Software Development: RE: Can't get DMA using low level driver working on DSP
- The crossbar to the EMIF is not great. Which CS space are you using for your transfer? The number of wait states changes with chip select space.
Transferring to IRAM may help you, as I believe the DMA will transfer from EMIFA to CPU... - MW 08:10 AM FPGA Development: RE: uPP receive issues
- Do you know which two byes you are missing? Are they consistently the same two bytes?
Do you have a chipscope license?
10/24/2013
- SH 08:10 PM Software Development: RE: Can't get DMA using low level driver working on DSP
- I hope somebody is still monitoring this thread - I have DMA working now using buffers on the FPGA, but the transfers seem to be pretty slow. I am transferring 228 16 bit words from the FPGA buffers (so over the EMIF). I am using the h...
- SH 10:54 AM Software Development: RE: SYS/BIOS and SYSLINK
- Hi Mike:
Here is another example of why I think the move to SYS/BIOS is necessary - check out this post:
http://e2e.ti.com/support/development_tools/code_composer_studio/f/81/p/3205/116267.aspx
note the key phrase - "RTDX no lon...
10/23/2013
- MT 08:25 AM FPGA Development: RE: uPP receive issues
- I have updated my source code
This is my *.ucf file
NET "o_upp_2xtxclk" LOC = "F4" | IOSTANDARD = LVCMOS18;
NET "io_upp_chb_clock" LOC = "T1" | IOSTANDARD = LVCMOS18;
NET "io_upp_chb_start" LOC = "T2" | IOSTANDARD = LVCMOS18 | PU... - Hi,
I am using Upp to transfer data between FPGA and OMAP.
The data send from FPGA to OMAP is OK. But FPGA can not receive exactly data from OMAP.
FPGA has missed 2 byte from OMAP.
in FPGA design, i have used clock from OMAP to recei...
10/19/2013
- PS 10:38 AM Software Development: RE: UPP acquisition issue
- hi Greg,
Thanks a million for all the help, solved the issue finally. I did set the dma thread priority to 15 but that didn't help. Finally enabled STARTA and used it as a handshake signal between UPP and ADC, rather than using extern...
10/18/2013
- GG 02:09 PM Software Development: RE: UPP acquisition issue
- Hi Preejith,
First, in relation to the thread priority, 15 is the maximum priority for a task and 1 is the lowest. I think the confusion comes from that fact the priority for the DMA engine itself ranges from 0-7, with zero being the... - PS 10:12 AM Software Development: RE: UPP acquisition issue
- hi Greg,
We tried both your suggestions but without success. First about the DMA thread priority, we tried setting it to 15 but it didn’t change anything. According to what i understand from the dsp/bios manual it seems 0 is the highe... - MF 08:18 AM Software Development: RE: File transfer methods
- I did not try a ftp transfer. We have decided to do the transfer within our application, by connecting to a socket and just sending the file data through. I would expect to get performance something like netcat.
Mary
10/17/2013
- JC 04:07 PM Software Development: RE: File transfer methods
- Mary what do you get from the ftp server?
- GG 02:07 PM Software Development: RE: UPP acquisition issue
- Hi Preejith,
In the code you attached the Channel A and Channel B DMA thread priorities are set to 9. These can be set to a much higher priority (TSK_MAXPRI = 15 is the max). That might help.
One question I have is whether you ar... - We have an application where a 14 bit ADC is wired to the UPP port via the FPGA. The application needs to perform triggered acquisition and process the data acquired. Acquisition via UPP is initiated via a hardware interrupt which happen...
10/16/2013
- MF 09:48 AM Software Development: RE: File transfer methods
- I tried some tests as you suggested.
file size = 64 Mbytes
scp: 60 sec (using WinSCP)
sftp: 53 sec (using WinSCP)
tftp: 6 min (using TFTPServer)
netcat: 20 sec (Linux host)
I also tried compressing with gzip, but after ...
10/14/2013
- JC 02:51 PM Software Development: RE: File transfer methods
- Note that all of my experiments have been on a mitydsp copying from nand and not sata.
- JC 02:49 PM Software Development: RE: File transfer methods
- I built the latest busybox using instructions provided and ran the ftpd service as described below and got a transfer rate close to 6MB/s.
I copied the new busybox executable to the /home/root folder and ran it from there for the belo... - MW 02:28 PM Software Development: RE: File transfer methods
- TFTP is not very efficient depending on how it is configured.
- MW 02:27 PM Software Development: RE: File transfer methods
- It might be easier to export the mitydsp filesystem via NFS or SAMBA and have windows access it directly.
Or have the mitydsp mount a windows share via SAMBA and do a copy.
You should be able to get 7 or 8 MB/sec transfer speeds,... - JC 02:23 PM Software Development: RE: File transfer methods
- I was able to transfer a 6MB file in about 13 seconds which is about 472 kB/s.
And the same transfer done over scp took about 6 seconds and reported an average speed of 1.0MB/s. - JC 02:14 PM Software Development: RE: File transfer methods
- I switched to using the http://tftpd32.jounin.net/ program as the tftp server as I was unable to get the other one to give me enough data to determine transfer speed. This program is much simpler and will display the transfer speed of t...
- JC 02:06 PM Software Development: RE: File transfer methods
- My guess is that windows firewall is blocking the connection. You should be able to google how to allow an inbound connection through the firewall on port 69 for your specific version of windows.
-Jonathan - MF 01:58 PM Software Development: RE: File transfer methods
- Trying the Solar Winds tftp server. Installed it, ran it.
On my target:
root@mityomap:/mnt/sata# tftp -p -l testfile 192.168.1.82
tftp: timeout
root@mityomap:/mnt/sata# tftp -p -r testfile 192.168.1.82
tftp: timeout
Also t... - BD 01:53 PM Software Development: RE: File transfer methods
- Mary,
The angstrom distribution we use for our baseline does not include a TFTP server in its package repository.
If the TFTP speed meets your requirements, you will need to compile busybox and enable support for TFTPD.
Some t... - JC 01:25 PM Software Development: RE: File transfer methods
- It is possible. But i would test the other direction first to see if you get the speeds your looking for.
-Jonathan - MF 01:24 PM Software Development: RE: File transfer methods
- The Windows PC would be requesting the file. So, I think we want the som to be the server. Is this possible?
Mary - JC 01:16 PM Software Development: RE: File transfer methods
- Mary,
There should be a tftp dameon package available for this platform.
Which device will be triggering this transfer? Meaning is the Windows computer going to be the server and the som the client or visa versa.
If you want... - What is the most efficient file transfer method that this distro supports? We expect to generate very large files (up to 1 GB) on a SATA drive. A host PC (Windows) will need to transfer the files from the target to the host over a netw...
10/11/2013
- ZL 11:30 AM PCB Development: RE: MityDSP-L138F LVDS lengths? .... (posted on behalf of a customer)
- Hi Angela,
The following traces' length are reported from our tool.
Let us know if you need anything else. Thank you.
Net Name Trace Length (mil)
IO_7_N 892.248
IO_7_P 942.683
IO_9_N 859.358
IO_9_P 883.568 ... - TI 07:45 AM Software Development: RE: IndustrialIO board with Mity-DSP-L138F, No ETH PHY detected
- One thing that sticks out..
you flashed the kernel to 0x100000 instead of 0x10000 (which is where you erased).
which could explain the no magic # issue.
If the phy detection issue is limited to the SOM and you said there was an elec... - I am using an IndustrialIO Rev 2B board with a Mity-DSP-L138FI-236-RL SOM in which uboot reports:
Resetting ethernet phy
Net: No ETH PHY detected!!!
When investigated using "mii device", no names are listed. I think this indicat...
10/10/2013
- My company is using your MityDSP-L138F SoM in a research prototype. The design has a high speed LVDS bus to the Spartan-6. We need to design LVDS bus with an off module clock input connecting to the FPGA O-SERDES2. To clculate the cloc...
- MW 07:38 AM Software Development: RE: EMIFA write timing
- Hi Steven,
Using a separate chip select (and adjusting the wait timings setup in u-Boot) should make this feasible, but I can't really help much further with a detailed implementation.
If you are not using any of CL's provided core... - SH 12:52 AM Software Development: RE: EMIFA write timing
- To read the THS1206 I need two chip selects, which can be the core cs and an address bit. Then I need a read pulse which is enclosed within the chip selects and long enough that the THS1206 has time to drive the data bus so the EMIFA ca...
10/09/2013
- MW 01:36 PM Software Development: RE: EMIFA write timing
- Do you mean for the EMIFA from the OMAP-L138 or the signals from the EMIFA_iface.vhd module that CL provides?
I don't have one drawn up, but you do have the source code for the EMIFA_iface.vhd (if that is what you are after) that you ... - Is there a diagram for the EMIFA write timing like the one in the wiki for read timing? I am having some problems implementing an interface to a THS1206 ADC using RD and WR - for the read, it looks like RD goes high after everything is ...
10/08/2013
- SC 06:04 PM Software Development: RE: UPP "start" signal ignored in receive mode?
- FYI, for anyone reading this in the future:
The root of the problem was that the FPGA was sending longer or shorter packets than the UPP hardware was configured for. The START signal does actually work once everything is configured c... - DR 04:12 PM Software Development: RE: Can't get DMA using low level driver working on DSP
- You bring up a very good point. If you are only moving 16 words every 4us, the overhead to setup the DMA may be too much to make it worth doing that.
Do you have a latency requirement (i.e., how may microseconds from the time the dat... - SH 04:09 PM Software Development: RE: Can't get DMA using low level driver working on DSP
- By the way, David and Mike, thanks for the information on the cache functions. When I insert them into my example, I see that the data has indeed been transferred by DMA. Too bad I didn't do this a couple of days ago...
- SH 03:52 PM Software Development: RE: Can't get DMA using low level driver working on DSP
- Thanks, David for all that information - as you can tell I am not very experienced in DSP programming. I hope you won't mind if I ask you a related question. The reason for wanting to use DMA in the first place is that I must read 8 wor...
- DR 03:19 PM Software Development: RE: Can't get DMA using low level driver working on DSP
- The QDMA can be used for just about anything the EDMA can be used for, in terms of transfers, but it can't be triggered by an external event -- it is software triggered. What this means is that you have to have an interrupt handler to r...
- SH 01:30 PM Software Development: RE: Can't get DMA using low level driver working on DSP
- First to David Rice: This test was just meant to get me started - ultimately I want to transfer 16 bit words from external memory (via EMIFA mapped through the FPGA) from an ADC to internal memory for processing. So that once I got the ...
- MW 01:20 PM Software Development: RE: Can't get DMA using low level driver working on DSP
- Hello Steven,
Is it possible that you need to invalidate your cache prior to validating the transfer has completed? I am looking at your code and I do not see any invalidation. Are you disabling CACHE via the MAR registers or BIOS s... - DR 01:01 PM Software Development: RE: Can't get DMA using low level driver working on DSP
- Hi Steven,
I looked briefly at your code and nothing jumped out at me...
I am the one who developed Critical Link's QDMA class for use on this module, although it was a couple of years ago. I do remember that it was a very painful... - I desperately need some help here. I have been trying for 3 days to get DMA working on the DSP. I have attached a CCSv5.5 project that I have been working with – it couldn’t be much simpler, just a memory to memory transfer using the e...
10/07/2013
- MW 08:00 PM Software Development: RE: GPIO sharing between ARM and DSP
- Hi Steven,
We don't have any partitioning schemes in place, as it is very application specific. In fact, we don't have DSP based interrupt handling of OMAP-L138 GPIO's incorporated into our released DSP libraries because we don't hav...
10/06/2013
- SH 01:28 PM Software Development: RE: DSP DMA crashes Linux
- I too am having a lot of trouble implementing EDMA on the DSP using LLD. But I don't understand Lars' last post. As far as I can see, looking at the files in ../arch/arm/mach-davinci, the call to da850_register_edma() is not meant to h...
10/05/2013
- According to the information in this link:
http://e2e.ti.com/support/embedded/linux/f/354/t/47756.aspx
the linux side and the DSP side have to partition GPIO resources by bank. But the GPIO pins available on the MityDSP-L138F seem...
09/30/2013
- RK 12:36 PM Software Development: RE: DSP GPIO interrupts (No-FPGA)
- Hello Steven,
1. It is highly recommended to set the pins up in a matter you want to use them. The processor may be configured at a startup to have these pins as GPIO's, but this configuration can be changed by the other application, ... - MW 07:09 AM Software Development: RE: watchdog causes strange side effects
- Ah, OK.
There is a "post on TI's E2E site":http://e2e.ti.com/support/embedded/bios/f/355/t/74121.aspx that talks about this exact issue. The post also includes some example code to have the DSP use Timer 2 or Timer 3 instead of tim... - SB 06:44 AM Software Development: RE: watchdog causes strange side effects
- Got some more insight. When I start kicking the watchdog, the dspbios function TSK_sleep() fails (sleeps forever). It seems that dspbios relies on the same timer as the watchdog. How can I select which timer is used by dspbios and linux ?
09/29/2013
- SB 04:24 PM Software Development: RE: watchdog causes strange side effects
- Thanks for the fast reply !
Model #:L138-FI-381RL-3B
/proc/config.gz attached
Further debugging revealed that the communication between ARM and DSP stops as soon as I start kicking the watchdog. The DSP is still alive, but it appe... - MW 07:53 AM Software Development: RE: watchdog causes strange side effects
- Is it possible the watchdog is firing before you kick it? How much margin do you have between the kick and the configured timeout?
-Mike
- MW 07:51 AM Software Development: RE: watchdog causes strange side effects
- None come to mind right away....
What model number SOM are you using?
What version of the kernel are you using, and can you attach your /proc/config.gz file?
Also, do you have a simple application that reproduces the issue that ... - BK 03:01 PM Software Development: RE: Audioexample with DSP-ARM-Communication
- Hej Mike,
if your support is for DSPBios and DSPLink and there is no much overhead, then I will stick to that.
The main reason for using a McBSP is that I plan two options for the system. One using the MityDSP-FPGA to route the aud... - MW 09:09 AM Software Development: RE: Audioexample with DSP-ARM-Communication
- DSPBIOS (or SYSBIOS) does not introduce much overhead, it should be fine for you application. If you need to, you could do your DSP processing in an interrupt handler to avoid context switching, but I suspect that a simple task based sy...