Activity
From 08/05/2013 to 09/03/2013
09/03/2013
- TI 06:14 PM Software Development: RE: Graceful shutdown at what level?
- Helmut
I would think you could use the linux power management features to do this. Much like you can push a button on your laptop or PC to have it turn off.
See https://wiki.archlinux.org/index.php/Power_Management for an example. You ... - MW 06:03 PM Software Development: RE: Graceful shutdown at what level?
- Well,
Some questions come to mind as you have a couple of isses.
- Is your application writing anything to the filesystem (assuming a NAND based implementation) and what filesystem are you using (JFFS2)? If it's not writing anyt... - I've inherited someone else's hardware design, based on the Critical Link OMAP-L138F SoM, and I must finish up the software.
I need to code graceful shutdown based on a pushbutton controller and battery voltage monitor. I see three p... - SH 02:04 PM Software Development: RE: Programming fpga from inside ARM application
- Thanks, Mike. I am running linux, and the system() call was just what I was looking for.
09/02/2013
- MW 08:36 AM Software Development: RE: Programming fpga from inside ARM application
- Is the ARM an linux application or a bare metal application?
If it is a linux application, you will need to write a custom driver (if our driver isn't good enough to suit your needs) as you need direct access to the EMIFA bus and GPIO...
08/30/2013
- We have examples of how to program the FPGA from uboot or from the linux command prompt. I have used both methods successfully. However, for various reasons I would like to load the image file into the FPGA from a running application ...
- CR 11:15 AM Software Development: RE: OMAPL138 DSP-EDMA3 transfer from EMIFA when Linux is running on ARM
- Another update...
Now Ti reports that I have to say the linuxkernel to reserve the DMA-channels what I using on the dsp. In my case channel 26 on CC1. I did this by getting out the following code from the "board-da850-evm.c" and put i... - CR 08:20 AM Software Development: RE: OMAPL138 DSP-EDMA3 transfer from EMIFA when Linux is running on ARM
- I got an response from TI. this behavior has probably something to do with the used IRQ channel on ARM side. ARM uses IRQ 93 and 94 which are related to the EDMA3CC1. This is the CC what I use. Only for testing purpose, I want to deactiv...
08/29/2013
- MW 08:31 PM Software Development: RE: tcDspFirmware::print_version_info() writes past end of buffer
- Hi John,
Thanks for the information, we'll patch this up for the next release. I'm very sorry for the bug (and curious why our SA tool didn't catch this one).
-Mike
- print_version_info() can write more bytes than the 'anMaxLen' argument. The workaround is to pass it a large enough buffer, one that holds the full version string.
Details:
The declaration is
static void print_versio... - CR 07:38 AM Software Development: RE: OMAPL138 DSP-EDMA3 transfer from EMIFA when Linux is running on ARM
- Thanks Mike for your quick answer!
I don't think so that it has something with my used timer(Timer64P3) to do. I put the suspend source of this timer to the DSP and when i stop the DSP with the debugger, the ARM system is well running... - MW 07:14 AM Software Development: RE: OMAPL138 DSP-EDMA3 transfer from EMIFA when Linux is running on ARM
- I suspect that linux may be using the same EDMA resources or interrupts.
I think that the linux ARM-9 port may use a timer and interrupt for generating it's local scheduler clock. You might try a different timer.
-Mike
- Hi,
I'm not sure if this forum is the right place to post this question but i will do it an hopefully anybody can help me.
First I developed my DSP-application without having the Linux an the ARM core running. The DSP app shell cop...
08/28/2013
- 华罗 05:37 AM PCB Development: RE: The schematic of MityDSP-L138 Development Kit
- Hi,tom
please e-mail me the link to download the design files for the MityDSP-L138F schematic,thx!
08/26/2013
- MF 02:08 PM Software Development: RE: EMIFA Clock not present
- The clock started working after some FPGA machinations.
New problem:
We can read registers from the FPGA but can't write:
Here's the code on the ARM side:
08/24/2013
- RK 10:11 AM Software Development: RE: DSP EDMA IRAM DATA TRANSFER
- Solved !
The problem was in the declaration of arrays to which I have copied the content of pointers. If you generally stick to these rules:
-Declare static pointers and initialize their values in the DSP/BIOS task
-Do not modify ...
08/23/2013
- The tcDspFpgaStepper class has a SetInterruptEnable() method that wasn't in MDK 2.11.
If you create your instance of tcDspFpgaStepper with apConfig->mbEnable set to true (explicitly or by default), interrupts are enabled.
If you create... - MW 07:33 AM Software Development: RE: handover I2C bus control from ARM to DSP
- The I2C0 bus (I believe), according to the datasheet, controls both the factory configuration data as well as a Power Management IC (PMIC).
The PMIC is used by the kernel to adjust the core voltage from 1.2 V to 1.3 V in order to supp...
08/20/2013
- Hi,
I am working with the mity L138 board, running Angstrom linux on the ARM and dspbios on the DSP. Currently, the ARM is controlling the I2C bus, using the built in I2C driver. I want the DSP to control the I2C bus, the ARM should n... - MF 10:26 AM Software Development: RE: EMIFA Clock not present
- We are baffled. I have checked the following registers using a JTAG emulator (Blackhawk USB560 on the DSP side).
The hardware is MityDSP-OMAPL138 SOM without FPGA attached to an Industrial I/O board. This kernel is your MDK_2012-08-... - JC 08:49 AM Software Development: RE: Printf when application loads and starts on boot-up
- The short answer is yes. The long answer is just give it a shot, you never know what you might learn. :)
-Jonathan
08/19/2013
- According to the FAQ on "How do I make my application run automatically on startup" there will not be a controlling terminal. But will printf statements still go to the standard serial output? This would be useful for seeing what is ha...
08/15/2013
- SH 02:50 PM FPGA Development: RE: Problem programming FPGA with Linux driver
- I guess I spoke too soon. I am still having this problem - with working FPGA code, sometimes I can get the cores to enumerate using echo "3" and sometimes it will not work. Small changes in the code of my custom core that appear to have...
- SH 12:34 PM FPGA Development: RE: Problem programming FPGA with Linux driver
- I think I figured out the source of the problem myself. Although I didn't change anything in the module files for base and emifa, in my top module port map for the base module I had disabled the "i_irq_map" and "o_irq_output" connection...
- BD 12:42 PM Software Development: RE: No DVI and serial output from MityDsp-L138 Industrial I/O board
- I'm glad it's working Phil. I'm locking this thread, but if you have any other questions, please let us know.
Thanks,
-Bob
- PC 10:29 AM Software Development: RE: No DVI and serial output from MityDsp-L138 Industrial I/O board
- Hi Bob,
There is no "Null Modem" printed on the serial cable provided with the dev kit. It works now after I put a null modem adapter on the cable. Thanks for prompt response.:)
Phil
08/14/2013
- SH 06:57 PM FPGA Development: RE: Problem programming FPGA with Linux driver
- I am using the Critical Link framework - the base module and the EMIFA interface are untouched.
- MW 06:08 PM FPGA Development: RE: Problem programming FPGA with Linux driver
- If you are not using our framework (the base module, specifically), then the state will report failed as it is probing the base module for valid versioning information. Are you using the base module or have you implemented your own EMIF...
- I'm having a problem programming the FPGA using the Linux driver. I am generating a core bin file using IMPACT, and the sequence of loading the file seems to execute with no problems - the "DONE" LED goes on, and I can see with a scope ...
- BD 06:02 PM Software Development: RE: No DVI and serial output from MityDsp-L138 Industrial I/O board
- Phil, can you confirm that the serial cable provided with the dev kit has "Null Modem" printed on each connector?
Can you use ssh to connect (not telnet)?
Thanks,
-Bob
- We just got the board from Digi-key.
Module Part Number: L138-FX-225-RC S/N: 110174
I/O Board Number: 80-000268RI-2B S/N: 123981
There is no DVI and serial output when power up. Ethernet is up and I can ping the IP but not teln... - CB 02:13 PM PCB Development: RE: MityDSP-L138 base board schematic
- At the moment I'm using the Industrial IO board and stopping the ARM in uBoot, so I can prototype DSP code.
Eventually however I will need to disable the Arm core and write my own boot loader in the DSP to setup the SOM memories and ... - MW 02:02 PM PCB Development: RE: MityDSP-L138 base board schematic
- The SOM schematics are not directly available. You should contact Tom Catalino if you require additional information beyond the data sheet and the PCB design guide.
Is there any specific question I can answer?
-Mike
- CB 02:00 PM PCB Development: RE: MityDSP-L138 base board schematic
- I have the Industrial IO board schematic I am trying to find the SOM schematics.
Sorry for the confusion,
Chris. - MW 01:56 PM PCB Development: RE: MityDSP-L138 base board schematic
- Use this link:
"http://support.criticallink.com/redmine/projects/indio/wiki/Industrial_IO_Revision_Information":http://support.criticallink.com/redmine/projects/indio/wiki/Industrial_IO_Revision_Information
Take the latest schemati... - Hi,
I'm designing a carrier board for the MityDSP-L138 and was wondering where I could download the MityDSP-L138 base board schematics.
Thanks,
Chris. - MF 10:36 AM Software Development: RE: EMIFA Clock not present
- Yes, we are using non-FPGA modules. Double checked the schematic, reprobed, tried different SOM modules, checked the clock on your Industrial IO board. Still no clock.
We are doing asynchronous read/writes to our own FPGA and just n... - RK 09:43 AM Software Development: RE: DSP EDMA IRAM DATA TRANSFER
- Hello again,
Basically I am trying to access an address space defined in my .tcf file (identical with DSP-side HelloWorld DSP/BIOS project) as CACHE_L2, whose base address is 0x11820000 and whose length is 0x00020000. I am basically try...
08/13/2013
- MT 10:48 PM FPGA Development: RE: Programming FPGA on power up issues
- Hi,
We have resolved that issues.
We used EDK system to develop FPGA and we modified bitgen.ut below:
-g TdoPin:PULLNONE
#-g StartUpClk:JTAGCLK
-g DriveDone:YES
before that: we use -g StartUpClk:JTAGCLK and -g TdoPin:PULLNON... - MW 06:33 PM FPGA Development: RE: Programming FPGA on power up issues
- Hi,
Sorry for the delay, are you still having issue here? Or have you solved the issue?
Can you dump your u-boot text when you try to program?
-Mike
- MW 06:35 PM Software Development: RE: DSP EDMA IRAM DATA TRANSFER
- 0x11822000 is not in DDR space, are you trying to access local SRAM or DDR?
-Mike
- MW 05:27 PM Software Development: RE: EMIFA Clock not present
- Hmm.... The EMA_CLK output should be active on power up, is it possible on your customer board there is contention. There is a 50 Ohm series resistor in line on the module side. You are using a non-FPGA based module, right?
Changin... - The EMIFA clock is not active on our custom board. This signal goes high and stays there. This is true after booting Linux or just U-boot.
Here's the U-boot log: - JC 09:31 AM Software Development: RE: Problems with custom board
- Thanks for the update.
-Jonathan - MF 09:29 AM Software Development: RE: Problems with custom board
- The problem was the GPIO. We had set the two I2C io pins as GPIO. I removed these from the list in the custom board support file, and it boots normally.
Thanks,
Mary - MW 09:11 AM Software Development: RE: DSP connection to FPGA cores
- Yes.
08/12/2013
- SH 07:12 PM Software Development: RE: DSP connection to FPGA cores
- Should I assume that, since I have not had a reply to my last message, my comments in that message are correct?
08/11/2013
- SH 10:03 PM Software Development: RE: DSP connection to FPGA cores
- Thanks for a very quick reply. So if I read or write from 0x66xxxxxx I will generate CS5 and if I read/write from 0x64xxxxxx I will generate CS4? Then if I route the interrupt output from my FPGA core to any of the GP0_0 through GP0_15...
- MW 07:17 PM Software Development: RE: DSP connection to FPGA cores
- I don't understand what you mean by "I can't use memory mapping as this is only useful for the ARM processor.".
The DSP (DSP/BIOS or SYS BIOS or bare metal code) can access the FPGA the same way as the ARM can. Just access the FPGA m... - For previous history, see the various messages and replies in "Simple Example Needed" below. I was able to get a custom core running and operating correctly using memory mapping, connecting to the ARM half of the OMAP. But now I am fac...
08/09/2013
- MW 09:18 AM Software Development: RE: RTC issue?
- Hi Kevin,
Would you be willing (offline) to share your schematics so that we might take a peek?
It's not obvious why you are having issues here.
-Mike
08/06/2013
- JC 11:15 AM Software Development: RE: Watchdog
- Yes,
You'd want to compile the davinci watchdog kernel module. - Is there a watchdog timer implemented in the MityDSP configuration anywhere that would restart Linux should the system go unresponsive? Thanks, Fred
- MT 07:21 AM FPGA Development: RE: Programming FPGA on power up issues
- I have done 2 way CPU,Linux and u-Boot. But result is the same.
- MW 07:15 AM FPGA Development: RE: Programming FPGA on power up issues
- How are you loading via CPU, linux or via u-Boot?
- Hi,
I am using MityDSP-L138F(LX16 FPGA) and Carrier Board.
I developed new FPGA system that included only Upp Interface, DCM (Input clock: 100MHz, output clock 75MHz) (I removed base_module, emif interface ,...) can be connect with OMA...
08/05/2013
- KR 11:32 AM Software Development: RE: RTC issue?
- I've check with the HW designer and he thinks it should be OK, see his info below
"The 3V_RTC pin of the L138 Module is at 2.7V when powered off. The design worst case should be 2.6V.
This is greater than the 2.5V that I believe is... - MW 11:08 AM Software Development: RE: RTC issue?
- Have you measured the Battery Backup voltage on your board through a power cycle? If the backup voltage drops below the required threshold, I think the RTC CTRL register resets to a disabled state.
-Mike
- Hi,
We are seeing an issue with the L138 RTC not running on our custom board - using hwclock we never see the time change.
I did some investigation and it looks like the SET32COUNTER bit in the RTC CTRL REG is always set after boot... - RK 06:18 AM Software Development: RE: Calculating FFT using SigProcTIDspSupport in SigProc library
- Hello,
It was the cause-thank you very much.It works. Curious enough, I now realised that the corrected implementation of SigProcTIDspSupport example works well now, whereas my SigProcFFT implementation returns the spikes with incorrect...