Activity
From 07/23/2013 to 08/21/2013
08/20/2013
- Hi,
I am working with the mity L138 board, running Angstrom linux on the ARM and dspbios on the DSP. Currently, the ARM is controlling the I2C bus, using the built in I2C driver. I want the DSP to control the I2C bus, the ARM should n... - MF 10:26 AM Software Development: RE: EMIFA Clock not present
- We are baffled. I have checked the following registers using a JTAG emulator (Blackhawk USB560 on the DSP side).
The hardware is MityDSP-OMAPL138 SOM without FPGA attached to an Industrial I/O board. This kernel is your MDK_2012-08-... - JC 08:49 AM Software Development: RE: Printf when application loads and starts on boot-up
- The short answer is yes. The long answer is just give it a shot, you never know what you might learn. :)
-Jonathan
08/19/2013
- According to the FAQ on "How do I make my application run automatically on startup" there will not be a controlling terminal. But will printf statements still go to the standard serial output? This would be useful for seeing what is ha...
08/15/2013
- SH 02:50 PM FPGA Development: RE: Problem programming FPGA with Linux driver
- I guess I spoke too soon. I am still having this problem - with working FPGA code, sometimes I can get the cores to enumerate using echo "3" and sometimes it will not work. Small changes in the code of my custom core that appear to have...
- SH 12:34 PM FPGA Development: RE: Problem programming FPGA with Linux driver
- I think I figured out the source of the problem myself. Although I didn't change anything in the module files for base and emifa, in my top module port map for the base module I had disabled the "i_irq_map" and "o_irq_output" connection...
- BD 12:42 PM Software Development: RE: No DVI and serial output from MityDsp-L138 Industrial I/O board
- I'm glad it's working Phil. I'm locking this thread, but if you have any other questions, please let us know.
Thanks,
-Bob
- PC 10:29 AM Software Development: RE: No DVI and serial output from MityDsp-L138 Industrial I/O board
- Hi Bob,
There is no "Null Modem" printed on the serial cable provided with the dev kit. It works now after I put a null modem adapter on the cable. Thanks for prompt response.:)
Phil
08/14/2013
- SH 06:57 PM FPGA Development: RE: Problem programming FPGA with Linux driver
- I am using the Critical Link framework - the base module and the EMIFA interface are untouched.
- MW 06:08 PM FPGA Development: RE: Problem programming FPGA with Linux driver
- If you are not using our framework (the base module, specifically), then the state will report failed as it is probing the base module for valid versioning information. Are you using the base module or have you implemented your own EMIF...
- I'm having a problem programming the FPGA using the Linux driver. I am generating a core bin file using IMPACT, and the sequence of loading the file seems to execute with no problems - the "DONE" LED goes on, and I can see with a scope ...
- BD 06:02 PM Software Development: RE: No DVI and serial output from MityDsp-L138 Industrial I/O board
- Phil, can you confirm that the serial cable provided with the dev kit has "Null Modem" printed on each connector?
Can you use ssh to connect (not telnet)?
Thanks,
-Bob
- We just got the board from Digi-key.
Module Part Number: L138-FX-225-RC S/N: 110174
I/O Board Number: 80-000268RI-2B S/N: 123981
There is no DVI and serial output when power up. Ethernet is up and I can ping the IP but not teln... - CB 02:13 PM PCB Development: RE: MityDSP-L138 base board schematic
- At the moment I'm using the Industrial IO board and stopping the ARM in uBoot, so I can prototype DSP code.
Eventually however I will need to disable the Arm core and write my own boot loader in the DSP to setup the SOM memories and ... - MW 02:02 PM PCB Development: RE: MityDSP-L138 base board schematic
- The SOM schematics are not directly available. You should contact Tom Catalino if you require additional information beyond the data sheet and the PCB design guide.
Is there any specific question I can answer?
-Mike
- CB 02:00 PM PCB Development: RE: MityDSP-L138 base board schematic
- I have the Industrial IO board schematic I am trying to find the SOM schematics.
Sorry for the confusion,
Chris. - MW 01:56 PM PCB Development: RE: MityDSP-L138 base board schematic
- Use this link:
"http://support.criticallink.com/redmine/projects/indio/wiki/Industrial_IO_Revision_Information":http://support.criticallink.com/redmine/projects/indio/wiki/Industrial_IO_Revision_Information
Take the latest schemati... - Hi,
I'm designing a carrier board for the MityDSP-L138 and was wondering where I could download the MityDSP-L138 base board schematics.
Thanks,
Chris. - MF 10:36 AM Software Development: RE: EMIFA Clock not present
- Yes, we are using non-FPGA modules. Double checked the schematic, reprobed, tried different SOM modules, checked the clock on your Industrial IO board. Still no clock.
We are doing asynchronous read/writes to our own FPGA and just n... - RK 09:43 AM Software Development: RE: DSP EDMA IRAM DATA TRANSFER
- Hello again,
Basically I am trying to access an address space defined in my .tcf file (identical with DSP-side HelloWorld DSP/BIOS project) as CACHE_L2, whose base address is 0x11820000 and whose length is 0x00020000. I am basically try...
08/13/2013
- MT 10:48 PM FPGA Development: RE: Programming FPGA on power up issues
- Hi,
We have resolved that issues.
We used EDK system to develop FPGA and we modified bitgen.ut below:
-g TdoPin:PULLNONE
#-g StartUpClk:JTAGCLK
-g DriveDone:YES
before that: we use -g StartUpClk:JTAGCLK and -g TdoPin:PULLNON... - MW 06:33 PM FPGA Development: RE: Programming FPGA on power up issues
- Hi,
Sorry for the delay, are you still having issue here? Or have you solved the issue?
Can you dump your u-boot text when you try to program?
-Mike
- MW 06:35 PM Software Development: RE: DSP EDMA IRAM DATA TRANSFER
- 0x11822000 is not in DDR space, are you trying to access local SRAM or DDR?
-Mike
- MW 05:27 PM Software Development: RE: EMIFA Clock not present
- Hmm.... The EMA_CLK output should be active on power up, is it possible on your customer board there is contention. There is a 50 Ohm series resistor in line on the module side. You are using a non-FPGA based module, right?
Changin... - The EMIFA clock is not active on our custom board. This signal goes high and stays there. This is true after booting Linux or just U-boot.
Here's the U-boot log: - JC 09:31 AM Software Development: RE: Problems with custom board
- Thanks for the update.
-Jonathan - MF 09:29 AM Software Development: RE: Problems with custom board
- The problem was the GPIO. We had set the two I2C io pins as GPIO. I removed these from the list in the custom board support file, and it boots normally.
Thanks,
Mary - MW 09:11 AM Software Development: RE: DSP connection to FPGA cores
- Yes.
08/12/2013
- SH 07:12 PM Software Development: RE: DSP connection to FPGA cores
- Should I assume that, since I have not had a reply to my last message, my comments in that message are correct?
08/11/2013
- SH 10:03 PM Software Development: RE: DSP connection to FPGA cores
- Thanks for a very quick reply. So if I read or write from 0x66xxxxxx I will generate CS5 and if I read/write from 0x64xxxxxx I will generate CS4? Then if I route the interrupt output from my FPGA core to any of the GP0_0 through GP0_15...
- MW 07:17 PM Software Development: RE: DSP connection to FPGA cores
- I don't understand what you mean by "I can't use memory mapping as this is only useful for the ARM processor.".
The DSP (DSP/BIOS or SYS BIOS or bare metal code) can access the FPGA the same way as the ARM can. Just access the FPGA m... - For previous history, see the various messages and replies in "Simple Example Needed" below. I was able to get a custom core running and operating correctly using memory mapping, connecting to the ARM half of the OMAP. But now I am fac...
08/09/2013
- MW 09:18 AM Software Development: RE: RTC issue?
- Hi Kevin,
Would you be willing (offline) to share your schematics so that we might take a peek?
It's not obvious why you are having issues here.
-Mike
08/06/2013
- JC 11:15 AM Software Development: RE: Watchdog
- Yes,
You'd want to compile the davinci watchdog kernel module. - Is there a watchdog timer implemented in the MityDSP configuration anywhere that would restart Linux should the system go unresponsive? Thanks, Fred
- MT 07:21 AM FPGA Development: RE: Programming FPGA on power up issues
- I have done 2 way CPU,Linux and u-Boot. But result is the same.
- MW 07:15 AM FPGA Development: RE: Programming FPGA on power up issues
- How are you loading via CPU, linux or via u-Boot?
- Hi,
I am using MityDSP-L138F(LX16 FPGA) and Carrier Board.
I developed new FPGA system that included only Upp Interface, DCM (Input clock: 100MHz, output clock 75MHz) (I removed base_module, emif interface ,...) can be connect with OMA...
08/05/2013
- KR 11:32 AM Software Development: RE: RTC issue?
- I've check with the HW designer and he thinks it should be OK, see his info below
"The 3V_RTC pin of the L138 Module is at 2.7V when powered off. The design worst case should be 2.6V.
This is greater than the 2.5V that I believe is... - MW 11:08 AM Software Development: RE: RTC issue?
- Have you measured the Battery Backup voltage on your board through a power cycle? If the backup voltage drops below the required threshold, I think the RTC CTRL register resets to a disabled state.
-Mike
- Hi,
We are seeing an issue with the L138 RTC not running on our custom board - using hwclock we never see the time change.
I did some investigation and it looks like the SET32COUNTER bit in the RTC CTRL REG is always set after boot... - RK 06:18 AM Software Development: RE: Calculating FFT using SigProcTIDspSupport in SigProc library
- Hello,
It was the cause-thank you very much.It works. Curious enough, I now realised that the corrected implementation of SigProcTIDspSupport example works well now, whereas my SigProcFFT implementation returns the spikes with incorrect...
08/04/2013
- DR 02:52 PM Software Development: RE: Calculating FFT using SigProcTIDspSupport in SigProc library
- I think your problem is here:
for(int i=0;i!=FFT_SIZE;i+=2)
{
mpWorkBuff[i]=sin21[i];
mpWorkBuff[i+1]=sin42[i];
}
Your indices for the two sin waves are incrementing by two, while they should be incremente... - Hello,
I am trying to compute the FFT from 2 signals at once. So far I managed to compute the FFTs of my signals basing on the SigProcFFT.cpp file with the commented example. However, for efficienty purposes(I am dealing with real-time ...
08/03/2013
- RK 03:47 PM Software Development: RE: DSP EDMA IRAM DATA TRANSFER
- Hello again,
Is there any way to set a variable to be stored in specific address ? Using the EDMA I have transferred a block of 2048 bytes, which now I would like to use as an array [2048] of chars further on in my program. I tried to d...
08/02/2013
- RK 04:31 PM Software Development: RE: DSP EDMA IRAM DATA TRANSFER
- Hello,
I added the line with _HWI_eventMap(anHWInterruptLevel, globalConfig[Edma3InstanceId].xferCompleteInt)_ in DspQDMA.cpp and rebuilt the library linked to my project. The transmission is done correctly. Second parameter was equal ... - MW 09:50 AM Software Development: RE: DSP EDMA IRAM DATA TRANSFER
- Heads up. Make sure that you configure the Event Mapper for the quick DMA transfer complete status to the DSP properly.
We found that we needed this patch to ensure the Event Mapper was routing the proper TCC interrupts from the ED... - JC 10:57 AM Software Development: RE: Problems with custom board
- Mary,
AUFS is a filesystem. It isn't a problem. Your .config file matches ours so doesn't appear to be the issue.
-Jonathan - MF 10:54 AM Software Development: RE: Problems with custom board
- The two baseboard entries don't sound like a problem:
- JC 10:40 AM Software Development: RE: Problems with custom board
- MF 10:07 AM Software Development: RE: Problems with custom board
- Thanks for the reply. We fixed the ethernet problem with a pullup on MII_RXD0, as was done on the industrial io board.
Attached is the .config file (renamed config).
Mary - MW 09:52 AM Software Development: RE: Problems with custom board
- You may not have the proper configuration options set for the Power Management and Voltage Regulators set in the kernel configuration. If those options aren't set, the voltage regulators won't be found and dynamic scaling will not work....
- JC 09:14 AM Software Development: RE: Problems with custom board
- According to your bootlog the following errors would cause the cpufreq directory to be missing as cvdd is needed.
08/01/2013
- I built a new kernel based on MDK_2012-08-10 starting with baseboard-industrialio.c and making a new baseboard file for our hardware. I mainly cut what we don't need and added support for SPI1, CS1.
I booted on the industrial io boar...
07/31/2013
- JC 02:34 PM Software Development: RE: mtd->read (...) returned ECC error
- Christian,
It is helpful for us if you create a new post so that we see it otherwise your might be missed. If you are still having this problem could you post your full boot log as well as the steps you took to create this problem.
... - RK 11:37 AM Software Development: RE: DSP EDMA IRAM DATA TRANSFER
- Hello,
In fact I did not and it was the cause. When I invoked the method, EDMA started to transfer data properly ! Thank you . Below is my corrected version, just in case someone would deal with similar problem:
tcDspQDMA * dm... - MW 10:26 AM Software Development: RE: DSP EDMA IRAM DATA TRANSFER
- Hi,
You need to make sure that you call tcDspQDMA::Initialize() with a free hardware level (try 7). Did you make that call?
-Mike
07/29/2013
- Hello,
I am currently programming the DSP of MitydspL138 Industrial IO Board using the DSP/BIOS. I am trying to transfer a block of data in IRAM, which I understand is a part of L2 cache of OMAPL138 processor. I am trying to use EDMA fo... - RK 09:41 AM Software Development: RE: DSP GPIO interrupts (No-FPGA)
- Hello again,
It works ! Invoking EventMap with an appropriate second argument solved the problem:
HWI_eventMap(6, 65);
Thank you very much.
Best regards
Rafal Krawczyk
- MW 08:43 AM Software Development: RE: DSP GPIO interrupts (No-FPGA)
- For the DSP Event Map (item number 1), refer to table 3-1 of the TRM in section 3.2.2.1.
GPIO Bank zero event appears to be 65. Looks like there is only one interrupt per bank.
For 2, check DspFirmware.cpp on how to set for rising... - RK 08:02 AM Software Development: RE: DSP GPIO interrupts (No-FPGA)
- A little corrction in what I have written in my previous mail- for bank 0 offset 0 (J701 pin 25) the function call shlould be: GPIOIntTypeSet(SOC_GPIO_0_REGS, 1, GPIO_INT_TYPE_RISEDGE): 16*0 +0 +1 . Still, it is not working.
Best rega... - RK 07:43 AM Software Development: RE: DSP GPIO interrupts (No-FPGA)
- Hello again,
First of all,thank you for your quick reply.
I am trying to implement the solution focusing on your advices. So far, it is not working. Here is what I did.
From the beginning:
*1) Configuring the DSP Event Map:*
I i...
07/28/2013
- MW 08:19 PM Software Development: RE: DSP GPIO interrupts (No-FPGA)
- Hi,
So currently the DspGpio.cpp implementation (for non-FPGA GPIO's) for the 674X core is does not implement interrupt handling (see the tcDspGpio::ConfigurePin() method in the source code). However, support could be added without t... - Hello,
I am currently programming the DSP using the DSP/BIOS . The problem I have is how to configure HWI in J701 pin 25 of MitydspL138 Industrial IO board. That is, I am trying to configure GPIO interrupts in non-FPGA pins. To config...
07/26/2013
- MW 11:33 AM Software Development: RE: Kernel bug
- Hi Mostafa,
Thank you for the notice.
I see that is in the master branch (2.6.34). We will correct it. However, it is not in the mitydsp-linux-v3.2 branch. You might consider upgrading to 3.2, most of our customers are using th... - Hi, just wanted to make you aware of a bug in the kernel sources:
http://support.criticallink.com/gitweb/?p=linux-davinci.git;a=blob;f=drivers/usb/gadget/epautoconf.c
lines 268 - 285 have been duplicated in lines 286 - 302.
-Mos...
07/24/2013
- MW 06:13 PM Software Development: RE: UPP "start" signal ignored in receive mode?
- Hi Stu,
Have you tried to use chipscope to confirm the alignment of the start strobe with the data as sent by the FPGA and check the UPP bus interface WAIT pins, etc? (if you don't have a license, I think you can get a 30 day trial on... - SC 12:53 PM Software Development: RE: UPP "start" signal ignored in receive mode?
- Scott,
Yes, we're trying to send one line (of 6176 bytes) per DMA memory buffer (also 6176 bytes). The "DspUpp.c" code seems to correctly handle setting up a "pending" DMA transaction behind the currently executing DMA transaction. ...
07/23/2013
- MW 05:52 PM Software Development: RE: UPP "start" signal ignored in receive mode?
- Hi Stu,
Check section 33.2.5.3 of the TRM. For receive mode, the start line is optional, controlled by the STARTx bit in UPICR.
The configuration of the strt signals are setup by the tsDspUppConfig in DspUpp.h and DspUpp.cpp. Che... - SW 04:56 PM Software Development: RE: UPP "start" signal ignored in receive mode?
- Stu,
I'm not sure about the DSP driver for uPP, I am using a Linux driver to the Arm. Are you trying to stream data from the FPGA to the DSP? Are you just using 1 line and therefore 1 memory buffer to transfer data via the uPP driver?...