Activity
From 07/14/2013 to 08/12/2013
08/12/2013
- SH 07:12 PM Software Development: RE: DSP connection to FPGA cores
- Should I assume that, since I have not had a reply to my last message, my comments in that message are correct?
08/11/2013
- SH 10:03 PM Software Development: RE: DSP connection to FPGA cores
- Thanks for a very quick reply. So if I read or write from 0x66xxxxxx I will generate CS5 and if I read/write from 0x64xxxxxx I will generate CS4? Then if I route the interrupt output from my FPGA core to any of the GP0_0 through GP0_15...
- MW 07:17 PM Software Development: RE: DSP connection to FPGA cores
- I don't understand what you mean by "I can't use memory mapping as this is only useful for the ARM processor.".
The DSP (DSP/BIOS or SYS BIOS or bare metal code) can access the FPGA the same way as the ARM can. Just access the FPGA m... - For previous history, see the various messages and replies in "Simple Example Needed" below. I was able to get a custom core running and operating correctly using memory mapping, connecting to the ARM half of the OMAP. But now I am fac...
08/09/2013
- MW 09:18 AM Software Development: RE: RTC issue?
- Hi Kevin,
Would you be willing (offline) to share your schematics so that we might take a peek?
It's not obvious why you are having issues here.
-Mike
08/06/2013
- JC 11:15 AM Software Development: RE: Watchdog
- Yes,
You'd want to compile the davinci watchdog kernel module. - Is there a watchdog timer implemented in the MityDSP configuration anywhere that would restart Linux should the system go unresponsive? Thanks, Fred
- MT 07:21 AM FPGA Development: RE: Programming FPGA on power up issues
- I have done 2 way CPU,Linux and u-Boot. But result is the same.
- MW 07:15 AM FPGA Development: RE: Programming FPGA on power up issues
- How are you loading via CPU, linux or via u-Boot?
- Hi,
I am using MityDSP-L138F(LX16 FPGA) and Carrier Board.
I developed new FPGA system that included only Upp Interface, DCM (Input clock: 100MHz, output clock 75MHz) (I removed base_module, emif interface ,...) can be connect with OMA...
08/05/2013
- KR 11:32 AM Software Development: RE: RTC issue?
- I've check with the HW designer and he thinks it should be OK, see his info below
"The 3V_RTC pin of the L138 Module is at 2.7V when powered off. The design worst case should be 2.6V.
This is greater than the 2.5V that I believe is... - MW 11:08 AM Software Development: RE: RTC issue?
- Have you measured the Battery Backup voltage on your board through a power cycle? If the backup voltage drops below the required threshold, I think the RTC CTRL register resets to a disabled state.
-Mike
- Hi,
We are seeing an issue with the L138 RTC not running on our custom board - using hwclock we never see the time change.
I did some investigation and it looks like the SET32COUNTER bit in the RTC CTRL REG is always set after boot... - RK 06:18 AM Software Development: RE: Calculating FFT using SigProcTIDspSupport in SigProc library
- Hello,
It was the cause-thank you very much.It works. Curious enough, I now realised that the corrected implementation of SigProcTIDspSupport example works well now, whereas my SigProcFFT implementation returns the spikes with incorrect...
08/04/2013
- DR 02:52 PM Software Development: RE: Calculating FFT using SigProcTIDspSupport in SigProc library
- I think your problem is here:
for(int i=0;i!=FFT_SIZE;i+=2)
{
mpWorkBuff[i]=sin21[i];
mpWorkBuff[i+1]=sin42[i];
}
Your indices for the two sin waves are incrementing by two, while they should be incremente... - Hello,
I am trying to compute the FFT from 2 signals at once. So far I managed to compute the FFTs of my signals basing on the SigProcFFT.cpp file with the commented example. However, for efficienty purposes(I am dealing with real-time ...
08/03/2013
- RK 03:47 PM Software Development: RE: DSP EDMA IRAM DATA TRANSFER
- Hello again,
Is there any way to set a variable to be stored in specific address ? Using the EDMA I have transferred a block of 2048 bytes, which now I would like to use as an array [2048] of chars further on in my program. I tried to d...
08/02/2013
- RK 04:31 PM Software Development: RE: DSP EDMA IRAM DATA TRANSFER
- Hello,
I added the line with _HWI_eventMap(anHWInterruptLevel, globalConfig[Edma3InstanceId].xferCompleteInt)_ in DspQDMA.cpp and rebuilt the library linked to my project. The transmission is done correctly. Second parameter was equal ... - MW 09:50 AM Software Development: RE: DSP EDMA IRAM DATA TRANSFER
- Heads up. Make sure that you configure the Event Mapper for the quick DMA transfer complete status to the DSP properly.
We found that we needed this patch to ensure the Event Mapper was routing the proper TCC interrupts from the ED... - JC 10:57 AM Software Development: RE: Problems with custom board
- Mary,
AUFS is a filesystem. It isn't a problem. Your .config file matches ours so doesn't appear to be the issue.
-Jonathan - MF 10:54 AM Software Development: RE: Problems with custom board
- The two baseboard entries don't sound like a problem:
- JC 10:40 AM Software Development: RE: Problems with custom board
- MF 10:07 AM Software Development: RE: Problems with custom board
- Thanks for the reply. We fixed the ethernet problem with a pullup on MII_RXD0, as was done on the industrial io board.
Attached is the .config file (renamed config).
Mary - MW 09:52 AM Software Development: RE: Problems with custom board
- You may not have the proper configuration options set for the Power Management and Voltage Regulators set in the kernel configuration. If those options aren't set, the voltage regulators won't be found and dynamic scaling will not work....
- JC 09:14 AM Software Development: RE: Problems with custom board
- According to your bootlog the following errors would cause the cpufreq directory to be missing as cvdd is needed.
08/01/2013
- I built a new kernel based on MDK_2012-08-10 starting with baseboard-industrialio.c and making a new baseboard file for our hardware. I mainly cut what we don't need and added support for SPI1, CS1.
I booted on the industrial io boar...
07/31/2013
- JC 02:34 PM Software Development: RE: mtd->read (...) returned ECC error
- Christian,
It is helpful for us if you create a new post so that we see it otherwise your might be missed. If you are still having this problem could you post your full boot log as well as the steps you took to create this problem.
... - RK 11:37 AM Software Development: RE: DSP EDMA IRAM DATA TRANSFER
- Hello,
In fact I did not and it was the cause. When I invoked the method, EDMA started to transfer data properly ! Thank you . Below is my corrected version, just in case someone would deal with similar problem:
tcDspQDMA * dm... - MW 10:26 AM Software Development: RE: DSP EDMA IRAM DATA TRANSFER
- Hi,
You need to make sure that you call tcDspQDMA::Initialize() with a free hardware level (try 7). Did you make that call?
-Mike
07/29/2013
- Hello,
I am currently programming the DSP of MitydspL138 Industrial IO Board using the DSP/BIOS. I am trying to transfer a block of data in IRAM, which I understand is a part of L2 cache of OMAPL138 processor. I am trying to use EDMA fo... - RK 09:41 AM Software Development: RE: DSP GPIO interrupts (No-FPGA)
- Hello again,
It works ! Invoking EventMap with an appropriate second argument solved the problem:
HWI_eventMap(6, 65);
Thank you very much.
Best regards
Rafal Krawczyk
- MW 08:43 AM Software Development: RE: DSP GPIO interrupts (No-FPGA)
- For the DSP Event Map (item number 1), refer to table 3-1 of the TRM in section 3.2.2.1.
GPIO Bank zero event appears to be 65. Looks like there is only one interrupt per bank.
For 2, check DspFirmware.cpp on how to set for rising... - RK 08:02 AM Software Development: RE: DSP GPIO interrupts (No-FPGA)
- A little corrction in what I have written in my previous mail- for bank 0 offset 0 (J701 pin 25) the function call shlould be: GPIOIntTypeSet(SOC_GPIO_0_REGS, 1, GPIO_INT_TYPE_RISEDGE): 16*0 +0 +1 . Still, it is not working.
Best rega... - RK 07:43 AM Software Development: RE: DSP GPIO interrupts (No-FPGA)
- Hello again,
First of all,thank you for your quick reply.
I am trying to implement the solution focusing on your advices. So far, it is not working. Here is what I did.
From the beginning:
*1) Configuring the DSP Event Map:*
I i...
07/28/2013
- MW 08:19 PM Software Development: RE: DSP GPIO interrupts (No-FPGA)
- Hi,
So currently the DspGpio.cpp implementation (for non-FPGA GPIO's) for the 674X core is does not implement interrupt handling (see the tcDspGpio::ConfigurePin() method in the source code). However, support could be added without t... - Hello,
I am currently programming the DSP using the DSP/BIOS . The problem I have is how to configure HWI in J701 pin 25 of MitydspL138 Industrial IO board. That is, I am trying to configure GPIO interrupts in non-FPGA pins. To config...
07/26/2013
- MW 11:33 AM Software Development: RE: Kernel bug
- Hi Mostafa,
Thank you for the notice.
I see that is in the master branch (2.6.34). We will correct it. However, it is not in the mitydsp-linux-v3.2 branch. You might consider upgrading to 3.2, most of our customers are using th... - Hi, just wanted to make you aware of a bug in the kernel sources:
http://support.criticallink.com/gitweb/?p=linux-davinci.git;a=blob;f=drivers/usb/gadget/epautoconf.c
lines 268 - 285 have been duplicated in lines 286 - 302.
-Mos...
07/24/2013
- MW 06:13 PM Software Development: RE: UPP "start" signal ignored in receive mode?
- Hi Stu,
Have you tried to use chipscope to confirm the alignment of the start strobe with the data as sent by the FPGA and check the UPP bus interface WAIT pins, etc? (if you don't have a license, I think you can get a 30 day trial on... - SC 12:53 PM Software Development: RE: UPP "start" signal ignored in receive mode?
- Scott,
Yes, we're trying to send one line (of 6176 bytes) per DMA memory buffer (also 6176 bytes). The "DspUpp.c" code seems to correctly handle setting up a "pending" DMA transaction behind the currently executing DMA transaction. ...
07/23/2013
- MW 05:52 PM Software Development: RE: UPP "start" signal ignored in receive mode?
- Hi Stu,
Check section 33.2.5.3 of the TRM. For receive mode, the start line is optional, controlled by the STARTx bit in UPICR.
The configuration of the strt signals are setup by the tsDspUppConfig in DspUpp.h and DspUpp.cpp. Che... - SW 04:56 PM Software Development: RE: UPP "start" signal ignored in receive mode?
- Stu,
I'm not sure about the DSP driver for uPP, I am using a Linux driver to the Arm. Are you trying to stream data from the FPGA to the DSP? Are you just using 1 line and therefore 1 memory buffer to transfer data via the uPP driver?...
07/22/2013
- MA 03:52 PM FPGA Development: RE: EMA_WAIT and bus contention on L138F
- Hi Mike, relevant definitions from the header:
- MW 02:11 PM FPGA Development: RE: EMA_WAIT and bus contention on L138F
- Just for sanity,
Have you confirmed you are writing to the correct AEMIF registers? CE3 is the NAND, and you are hitting "AEMIF_A3CR" in the above. I get a little confused about the register numbering vs. the CS numbering. Just wan... - MA 01:42 PM FPGA Development: RE: EMA_WAIT and bus contention on L138F
- Hi Mike,
I've now also tried setting unused I/O to float and increasing both the TA and Read Hold to 4 cycles. I've verified the timing change with ChipScope but unfortunately it has had no effect on the JFFS2 warnings.
Attaching a... - We have an FPGA application for the MityDSP-138F board which transmits "packets" to the DSP through the UPP port. The packet consists of 16 bytes of header and 6160 bytes of signal data. The FPGA asserts the UPP "start" signal on the f...
- DG 01:25 AM Software Development: RE: Fail to mount Root FS from MicroSD card
- Ok, managed to fix the problem.
I have changed mityomapl138_mmc_get_ro() in board-mityomapl138.c to return(0) since MicroSD has no write protect pin.
07/21/2013
- DG 10:19 PM Software Development: RE: Fail to mount Root FS from MicroSD card
- Hello, Tim!
Comma makes no difference, I have tried.
I have got a little progress - I have changed bootargs as follows:
bootsd=mmcinfo; ext2load mmc 0:1 0xc0700000 /boot/uImage; run sdargs; bootm 0xc0700000
sdargs=setenv bootar... - TI 07:27 AM Software Development: RE: Fail to mount Root FS from MicroSD card
- Dmitry,
I believe yhou are missing a comma in your bootargs..
root=/dev/mmcblk0p1 rw rootwait
should be
root=/dev/mmcblk0p1 rw,rootwait
cheers
/Tim - Hello!
I am trying to mount Root FS from MicroSD card (ext2 formated).
Boot process fails with kernel panic.
My U-Boot environment:
bootargs=mem=96M console=ttyS1,115200n8 root=/dev/mtdblock0 rw rootwait
bootcmd=sf probe 0; sf rea...
07/18/2013
- SH 06:50 PM Software Development: RE: RS-485 problems
- Solved the problem myself - it turns out that either SER_RS485_RTS_ON_SEND or SER_RS485_RTS_AFTER_SEND must be defined for the toggle to work. The flag SER_RS485_RTS_BEFORE_SEND is not recognised by the compiler, and (1<<3) doesn't seem...
- SH 05:54 PM Software Development: RE: RS-485 problems
- OK, then it all makes sense. In spite of the way the connector is shown in the documentation I was assuming (never assume) that the pinout was the "normal" IDC connector pinout.
So we are left with the problem that the TX_ENB line (p... - MW 05:20 PM Software Development: RE: RS-485 problems
- Actually, I take that back. The pin out is illustrated in Figure 2 of the specification....
-Mike
- MW 05:13 PM Software Development: RE: RS-485 problems
- Ah,
I think I may see the problem. Those connectors are pinned (on our PCB) for use with a ribbon cable and a DB-9 IDC connector (like the one you are using for the console). So the pins are numbered 1-5 on 1 row and then 6-10 on th... - SH 05:08 PM Software Development: RE: RS-485 problems
- My board is 80-000268RI-2B, S/N 132541. I looked at the appropriate document on the page you referenced, and while it is not the same document I was originally looking at, the pins and connectors are the same.
- MW 04:59 PM Software Development: RE: RS-485 problems
- Hi Steven,
Let's make sure you are referencing the correct revision information for the board (it has been updated a few times since original publication).
Revision history and schematics for the Industrial I/O boards are available... - SH 04:07 PM Software Development: RE: RS-485 problems
I am looking at pins on J504, based on the Industrial IO Board rev C documentation
Curiously, only pins 1,2,3,4,5,9 and 10 have solder showing ... that does not fit with the documentation.
I see traces on the back of the board go...- SH 03:27 PM Software Development: RE: RS-485 problems
- OK, here is what I see:
mitydsp@mitydsp-VirtualBox:~/linux-davinci$ git branch
master
* mitydsp-linux-v3.2
mitydsp@mitydsp-VirtualBox:~/linux-davinci$ git log
commit f13cb8373517840670b06fafc1b381e934c5ac37
Author: Michael Will... - MW 03:24 PM Software Development: RE: RS-485 problems
- I am assuming it compiled OK.
Are you sure that the write() call is returning successfully? Can you send the full example, or modify the stand alone examples (in c) and try them?
Also, you should be able to just - JC 03:22 PM Software Development: RE: RS-485 problems
- Btw press q to escape @git log@.
- JC 03:21 PM Software Development: RE: RS-485 problems
- Steven,
Run the command @git branch@ to see which branch is selected. It should say mitydsp-linux-v3.2. When you run @git log@ you should see the UART2 change at the top.
-Jonathan - SH 03:18 PM Software Development: RE: RS-485 problems
- OK, I built the new kernel and flashed it to the MityDSP - now uname gives:
Linux mityomapl138 3.2.0+ #1 PREEMPT Thu Jul 18 11:44:18 PDT 2013 armv5tejl GNU/Linux
But, I am still not seeing any toggling of Tx lines or the TX_ENB lin... - SH 02:43 PM Software Development: RE: RS-485 problems
- Sorry - my mistake. I re-installed the toolchain and then realized that I had typed "CROSS-COMPILE" instead of "CROSS_COMPILE". Kernel generation seems to be working now.
It is necessary to have the incantations exactly correct! - SH 02:06 PM Software Development: RE: RS-485 problems
- I seem to have the same problems - here is the output from a new shell:
- MW 01:52 PM Software Development: RE: RS-485 problems
- You only use the HOST native CC, not the cross tools, to build the config file. It seems like you have a CC environment variable set and it's pointing to a native (x86) gcc.
Can you please launch a new shell and run the setup script?... - SH 01:41 PM Software Development: RE: RS-485 problems
- I'm getting errors when I try to build the kernel:
mitydsp@mitydsp-VirtualBox:~/linux-davinci$ make ARCH=arm CROSS-COMPILE=arm-angstrom-linux-gnueabi- uImage
scripts/kconfig/conf --silentoldconfig Kconfig
WRAP arch/arm/include/... - MW 11:26 AM Software Development: RE: RS-485 problems
- If you have our repository cloned already....
- SH 11:14 AM Software Development: RE: RS-485 problems
- A newbie question - How do I build this particular branch of the kernel?
- SH 10:34 AM Software Development: RE: RS-485 problems
- Thanks for your response. Here is what I get from uname:
Linux mityomapl138 3.2.0 #1 PREEMPT Wed May 15 09:16:03 EDT 2013 armv5tejl GNU/Linux
- MW 12:30 PM FPGA Development: RE: EMA_WAIT and bus contention on L138F
- One thought:
Is it possible the tri-state drive logic for the data lines off the FPGA is creating bus contention? Perhaps there is a bug in the EMIFA interface that is not parking/tri-stating the data lines soon enough after OE is de... - MA 12:24 PM FPGA Development: RE: EMA_WAIT and bus contention on L138F
- Hi Mike,
Thanks for the suggestions.
Not sure I understand what you mean by FPGA access bandwidth. It is being used to implement the frontend of a high speed wireless communication system so we are using the the bus pretty much con...
07/17/2013
- MW 09:17 PM Software Development: RE: RS-485 problems
- OK. I have added the patch to the mitydsp-linux-v3.2 branch. You should be able to at least see the Tx line toggle with your code.
If you can confirm you are getting normal output on the Tx lines, then we can tackle the TXE issue. ... - MW 08:55 PM Software Development: RE: RS-485 problems
- Hi Steven,
Sorry for the confusion. It's not a menuconfig item. There is a patch needed to enable the UART2 pin pinmuxes (it didn't appear to get ported to the 3.2 kernel).
I will post the patch (push it to the git mitydsp-linux... - SH 08:32 PM Software Development: RE: RS-485 problems
- How would anyone know this? I have looked at the config of the kernel I am using and you are correct, these pins are not mentioned in the .config file. I built the kernel based on the instructions in the wike, and there is nowhere the ...
- DG 07:05 PM Software Development: RE: RS-485 problems
- Hello,
Is is possible your kernel may not be setting up the ARM pin multiplexing for UART2? In your baseboard file [arch/arm/mach-davinci/baseboard-industrialio.c if your using the industrial IO build], you probably need something like: - SH 06:48 PM Software Development: RE: RS-485 problems
- I have attached the files defining the class and showing how I open the serial port. Then I just use standard write calls using termHandle.
- I am trying to get the RS-485 running on my Industrial I/O board with the L-138F. I'm using the example code in "send.c" posted in the forum thread "Write UART2 RS-485 API". Looking at the pins on J504 (6 = Tx, 1 = Tx_ENB) I am not see...
- MW 07:38 AM FPGA Development: RE: EMA_WAIT and bus contention on L138F
- Hello,
How much bandwidth are you using for the FPGA accesses? Have you looked with any sort of bus analyzer (perhaps in chip scope) to assess the access logic? If the WAIT pin is getting hit, the slowdown could also be the ECC logi...
07/16/2013
- We have a project which uses CS4 and CS5 to write and read data from a pair of FPGA FIFOs respectively. CS4 is used exclusively for writing while CS5 is used exclusively for reading. The config register settings are:
/* CS4 config...
07/15/2013
- SH 05:23 PM Software Development: RE: Simple example needed
- Thanks for the help. I decided to take a very simple approach and use mmap to access the FPGA, based on the mmap example. Instead of an interrupt, I will just poll - I don't really need the response speed of an interrupt.
07/14/2013
- MW 08:22 AM Software Development: RE: Simple example needed
- Answers to questions:
1. The reserved FPGA id's are in the file: $MDK/sw/common/fpga/core_ids.h. I would use core ID 255 and count down for additional ones.
2. Not really. Normally we suggest that you start (for the FPGA) with th...