Activity
From 04/22/2013 to 05/21/2013
05/21/2013
- JC 11:14 AM Software Development: RE: Open Embedded Core Process Release Date
- As of right now and the foreseeable future the bitbake process is not working.
Your best options for creating a custom filesystem image are to either:
1. Create an opkg file that modifies our base filesystem to match what you wan... - KR 10:48 AM Software Development: RE: Open Embedded Core Process Release Date
- Hi,
Sorry for the lack of detail,
I want to setup an Open Embedded/Angstrom build system for a product I'm working on to allow us to tailor the root filesystem image to our requirements.
Look at the ARM Wiki there are instruct... - JC 10:47 AM Software Development: RE: Open Embedded Core Process Release Date
- Are you refering to this other post?
http://support.criticallink.com/redmine/boards/10/topics/2573?r=2707
It appears we overlooked this post. Sorry about that. The easiest way I know of to setup the development environment is to fo... - JC 10:39 AM Software Development: RE: Open Embedded Core Process Release Date
- Kevin,
Have you seen this page [[Starter_Guide]]?
Also we just released a new MDK that contains an updated kernel and industrial io board filesystem.
http://support.criticallink.com/redmine/attachments/download/3047/release_2013-0... - Hi,
I'm trying to build a MityDSP Image from the currently released information/files without success,
I realize the details are preliminary on the Web Page "Installing Open Embedded Core" - is there any information on the next re... - BK 05:30 AM Software Development: RE: U-Boot ELF loader
- Mike, thanks for your reply.
I tried lminfo and it doesn't recognise the image. I attach a log of the u-boot commands used and a small dump of the file. Also a log from a PC application (readelf) which seems to decipher the header O...
05/20/2013
- YW 09:39 AM Software Development: RE: ethernet over USB don't work
- My problem is solved now.
Thanks a lot. - MW 08:45 AM Software Development: RE: U-Boot ELF loader
- You may need to provide an "entry point" argument to the linker to point to the location in memory that the code should jump to. Have you dumped out your elf headers? I think by default the entry point is 0 for linux apps as it will ge...
- BK 08:17 AM Software Development: RE: U-Boot ELF loader
- Jonathan,
Thanks for pointing me in the right direction. I have downloaded the latest MDK and installed u-boot. The bootelf command was there but appeared to not work. It attempted to jump to address 0x00000000 which was never going ...
05/19/2013
- YW 10:00 PM Software Development: RE: ethernet over USB don't work
- How to do this change ?
I could find the call "mityomapl138_usb_init(MUSB_OTG)" in which file ?
An odd thing is that when I changed nothing but some drivers option in menuconfig, rebuilt the kernel, the DRVVBUS pin was not driven. ...
05/17/2013
- WC 03:04 PM FPGA Development: RE: FPGA load verification
- Thanks Mike.
I'm troubleshooting using your suggestions. I'll let you know what I find.
- GG 10:23 AM Software Development: RE: Start Guide : Cannot build helloworld application with eclipse
- Hello,
Have you run the environment setup script: - KR 06:02 AM Software Development: RE: Open Embedded build error
- Hi,
Was there a resolution to this problem - I'm having the same problem.
Is it because mitydsp-preferred-revs.inc is pointing to
CLSVN_BASEURI_mityomapl138 ?= "svn://wanda/svn/mityomap/mityomapl138"
Is there external access...
05/16/2013
- HF 05:53 PM Software Development: RE: Video output blinks frequently
- FIXED! I changed VPIF DMA0/1 priority from 4 to 1 and the blinks went away. Thanks you, Mike.
-Helmut - JC 08:45 AM Software Development: RE: U-Boot ELF loader
- Bruce,
Elf support was added on the following commit.
http://support.criticallink.com/gitweb/?p=u-boot-mitydspl138.git;a=commit;h=664282611755f43d396887e3ba2c8f06e275ea86
The latest MDK should have this change and includes the lat... - Am I correct in thinking that the latest u-Boot has an ELF loader? I take it that this will load an ELF image into RAM that can then be executed.
Currently our boards have an old version of uBoot. Is the latest available for downloa...
05/15/2013
- HF 11:40 AM Software Development: RE: Video output blinks frequently
- Mike,
I'm using VPIF. It *might* also be the case that my interfering tasks are interfering because they're transferring 153600 byte buffers between the DSP and ARM, via proc_READ() and proc_WRITE(). These transfers are intended to ... - HF 11:10 AM Software Development: RE: Video output blinks frequently
- VPIF!
- HF 11:08 AM Software Development: RE: Video output blinks frequently
- Mike:
Thanks for the advice. FYI, this is same project as Wade Calcutt is working on, regarding FPGA loading properly.
Bumping up bus master DMA priority sounds like that for which I'm looking. I looked at the TRM, and please con... - MW 10:26 AM Software Development: RE: Video output blinks frequently
- I suspect that you need to increase the bus master DMA priority of the VPIF or LCDC peripherals (it's not clear to me which output you are using, VPIF or LCDC, sounds like maybe VPIF).
You can read up about the priorities in the "OMAP... - JC 10:24 AM Software Development: RE: Video output blinks frequently
- Helmut,
First thing is which version of the kernel are you running?
__uname -a__
Also the command __nice__ can be used to start applications in a lower priority.
http://www.manpagez.com/man/1/nice/
There is also a system call ... - My custom system is based on the MityOMAP-L138F.
At random times, but fairly frequently, my video output corrupts for a frame. The nature of the corruption is that a single line (perhaps the top line) is shifted part way across the s...
05/14/2013
- MW 10:43 AM FPGA Development: RE: FPGA load verification
- You might bring the DCM status lines (particularly the lock status) to a scope just to see if that is the core issue.
-Mike
05/13/2013
- WC 03:12 PM FPGA Development: RE: FPGA load verification
- Mike,
To my knowledge we're not changing the CPU frequency. That being said, one of the output messages during Linux boot is:
MityOMAPL138: setting max frequency to 456 MHz
But that doesn't necessarily mean the frequency was bum... - MW 01:09 PM FPGA Development: RE: FPGA load verification
- Wade,
The EMIFA output clock can change if the OMAP-L138 CPU frequencies are modified (the EMIFA output clock is one of the SYSCLOCK divider outputs on PLL0).
Is it possible you are changing the CPU frequency or messing with the PL... - WC 12:28 PM FPGA Development: RE: FPGA load verification
- Hi Mike,
Thanks for your response and troubleshooting suggestions.
To answer your questions:
*Are you using a DCM or PLL? What is your clock source?*
I'm using a DCM as the clock source. Its source is the 100MHz EMIFA clock and... - MW 12:12 PM FPGA Development: RE: FPGA load verification
- Hi Wade,
If you are getting the "done" light on the part, then the FPGA is loading correctly and it's 99.99999999999% likely a logic, or more likely a logic reset condition in the code. I only say this because we have never had a pro... - I'm using a MityDSP-L138F with an FPGA load that is a modified version of the example code provided in the Vision Dev Kit. As part of the modifications I stripped out the base module, EMIFA interface, etc. and used a modified version of ...
05/09/2013
- MW 03:48 PM Software Development: RE: GPIO interrupt in MityOMAP-L138F
- I am glad you were able to figure this out, and these notes are helpful. Thanks for posting them.
We have been struggling for the DSP to sort out an easier way to track and validate the IRQ routing for the DSP application. The DSPLI... - MC 02:58 PM Software Development: RE: GPIO interrupt in MityOMAP-L138F
- Hi Mike,
I successfully implemented an interrupt example using FPGA Gpio core and your core libraries on DSP.
Maybe is useful to someone to say how, because the documentation is too generic about this topic:
1- Assuming you have a ...
05/07/2013
- MW 07:08 AM Software Development: RE: ethernet over USB don't work
- If you want to force HOST mode, then you will need to rebuild the kernel and change the call from:
mityomapl138_usb_init(MUSB_OTG);
to
mityomapl138_usb_init(MUSB_HOST);
This will force host mode in the driver. I think when y... - MT 06:29 AM Software Development: RE: Problem with uPP in DLB
- Hi François,
I am a newbie, and trying to create Upp Loopback with MityDSP1810F board.
Can you give your Upp Loopback source code.
my email: tungdm@viettel.com.vn
Thank you very much!
Tungdm
05/06/2013
- YW 09:59 PM Software Development: RE: ethernet over USB don't work
- Sorry for late reply. Thanks for your help at first.
I have removed the RNDIS driver.
What I use is a USB2.0 ethernet adapter with smsc7500. And the adapter is full size USB port. It connects to usb0 on mityarm1808.
I connected ID p... - YW 09:59 PM Software Development: RE: ethernet over USB don't work
- Sorry for late reply. Thanks for your help at first.
I have removed the RNDIS driver.
What I use is a USB2.0 ethernet adapter with smsc7500. And the adapter is full size USB port. It connects to usb0 on mityarm1808.
I connected ID p...
05/04/2013
- DR 09:24 AM Software Development: RE: ethernet over USB don't work
- I think you are using the wrong approach to do this. The RNDIS driver (g_ether.ko) is to allow IP over USB and is a USB peripheral (not host) driver. It sets the USB port on the ARM to look like a remote Ethernet adapter to a PC that i...
05/03/2013
- Hi,
I'm using MityARM-1808 with my own carrier board.
It has a hi-speed USB 2.0 to ethernet controller(smsc7500) connected with USB0 on mityarm-1808.
I connected the smsc7500 to my PC.
I selected the smsc75xx drivers in menuconfig an...
05/02/2013
- MW 09:55 AM FPGA Development: RE: Verilog codes for MityDSP-L138F
- You can use verilog, the Xilinx tools support it. However, all of our refernece code is in VHDL.
It may be possible (with a licensed version of the ISE or Vivado tools from Xilinx) to do a mixed mode synthesis, but I have not tried i... - Hello,
I am a beginner with FPGA programming and MityDSP-L138F. I know the board currently uses VHDL. Can I write Verilog code for the board? If so, what do I need? I appreciate your response.
Quoc
04/30/2013
- MW 07:30 AM FPGA Development: RE: OFFSET constraint never passes timing
- Did not receive it.
04/29/2013
- EB 05:17 PM FPGA Development: RE: OFFSET constraint never passes timing
- I tried:
-shreg_extract = checked
-shreg_min_size = 5
No difference.
There is a DCM on i_ema_clk already.
Should there be a phase shift?
I sent you my project by email.
Let me know if you don't get it.
Our email is not workin... - MW 04:28 PM FPGA Development: RE: OFFSET constraint never passes timing
- If you have it disabled, then it won't happen. Try leaving it enabled and seeting min size to 5.
The other thing that could be done is to use a DCM on the EMIFA clock, which will allow you to deskew any delays in the clock routing.
... - EB 11:55 AM FPGA Development: RE: OFFSET constraint never passes timing
- Thanks Mike,
In Synthesis Properties, HDL Options, I have:
-shreg_extract = unchecked
-shreg_min_size = 3
I see that IOB FFs are being used (unless the signal was trimmed).
I also see that output and io pins are set to slow slew, ... - MW 10:46 AM FPGA Development: RE: OFFSET constraint never passes timing
- Sorry about the -3 vs -2 issue. We will correct that on our next release. However, several designs have been validated and close using -2 speedgrade (you should be able to confirm that with the reference project, I think) using ISE 13....
- EB 09:56 AM FPGA Development: RE: OFFSET constraint never passes timing
- The paths that are failing are from the pads to the EMIF module, I don't have any code connecting there.
Also, the Industrial I/O project that I started with selected a -3 device.
You're shipping with -2 devices, so I changed to that...
04/23/2013
- MW 01:55 PM FPGA Development: RE: OFFSET constraint never passes timing
- Hi,
Two things.
1) You don't need the OFFSET=OUT spec with our IP. It turns out there is an extra clock in the wait states for read cycles, so you really have 18 ns to get the data to the OMAP, not 8.
2) Check this "FPGA overvi... - TI 01:38 PM Software Development: RE: SATA mount point
- You can also run "udevadm monitor" to watch for udev activity.
- JC 01:29 PM Software Development: RE: SATA mount point
- Scott,
I'm not sure whats going on. I can't explain why one would work as expected and the other doesn't. Its possible that udev is mounting sda to /media/sda. Trying running a 'grep -r /media/sda /' to see if you can find the file... - SW 11:44 AM Software Development: RE: SATA mount point
- the mmc card does not affect the mounting. It behaves the same way with or without it. I don't know if there are any differences with the dev kits. They were all purchased around the same time. I have reflashed them with a new kernel ...
- JC 11:39 AM Software Development: RE: SATA mount point
- Just as a curiousity, have you tried to see if adding/removing the mmc card affects how the sata drive mounts. Its the only thing I noticed different between the files you posted.
Are there any other differences between the dev kits ... - SW 11:35 AM Software Development: RE: SATA mount point
- i am uploading 4 files both my /etc/fstab and the output of fdisk. This is from 2 different systems with different SATA drives on. thanks
- JC 11:24 AM Software Development: RE: SATA mount point
- Scott,
Could you attach your fstab for both machines as well as the output of 'fdisk -l'?
-Jonathan - _Hello,
I've got a few mityDSP developement kits and am attaching SATA SSD drives to them. They are formated EXT4 with 1 Partition. I have modified /etc/fstab to attempt to automount the drive to /media/sda1 and have created the /medi...
04/22/2013
- I am using the following timing constraints.
If I remember correctly, I started from the industrial I/O example and these were there.
NET "i_ema_clk" TNM_NET = "i_ema_clk";
TIMESPEC "TS_ema_clk" = PERIOD "i_ema_clk" 10 ns HIGH 50 %;...