Activity
From 03/11/2013 to 04/09/2013
04/09/2013
- MC 02:02 PM Software Development: RE: GPIO interrupt in MityOMAP-L138F
- Hi Mike,
thanks for fast reply!
The best would be an example using an fpga gpio pin and an omap pin, just to test the possibilities.
Does the .tcf configuration file has a role in configuring the interrupt based on an fpga gpio p...
04/08/2013
- MW 01:07 PM Software Development: RE: GPIO interrupt in MityOMAP-L138F
- Are you trying to use a FPGA GPIO or an OMAP-L138 GPIO?
The DspGpio.h class should provide access to the OMAP-L138 GPIOs from the DSP. The DspFpgaGpio.h class should be used to access FPGA based GPIO modules. Both classes are derive... - Hello all,
I need to hook a HWI to a GPIO pin in a DSP application.
I have some questions:
1- Do your core library provide any class to do that? I see DspFpgaGpio.h and Gpio.h, but they lack a bit of documentation, and I can't find ... - FT 12:49 PM Software Development: RE: L138 - DSP Timer interrupt question ...
- Mike,
Thanks for information. Always very intressting. I am reading the Day2_AM training document.
Here our current system. We are using UPP to get data from FPGA. There is a block of data around each 17 ms.
Correct me if I am w... - Hello,
I am using Virtual Box and MityDSP-L138_SDK_2012_06_13.eva image.
When I following Start Guide instruction step by step.
(1) Install Gcc toolchain 4.5.4
(2) Update Eclipse CDT
But when I build HelloWorld Application I get ...
04/07/2013
- MW 07:53 AM Software Development: RE: L138 - DSP Timer interrupt question ...
- Check the "Interrupt Handling - Delayed Branch Latency" section of the Day2_AM training presentation located in our "MityDSP-67XX project files folder":http://support.criticallink.com/redmine/projects/dsp-products/files.
It's for the ...
04/04/2013
- FT 04:27 PM Software Development: RE: L138 - DSP Timer interrupt question ...
- Mike,
Can you add more details regarding this statement: _The DSP loop optimization can create large interrupt latency as well (which can cause missed interrupts on things like large memory copies by the CPU, etc)._
For example, ... - JC 11:43 AM Software Development: RE: MityDSP-L138F Failure to Boot and Cannot Reset
- Also feel free to look through the wiki http://support.criticallink.com/redmine/projects/arm9-platforms/wiki
- JC 11:40 AM Software Development: RE: MityDSP-L138F Failure to Boot and Cannot Reset
- The username for the modules should be _root_
04/03/2013
- MT 10:16 PM Software Development: RE: MityDSP-L138F Failure to Boot and Cannot Reset
- Hi,
Thank you so much for supporting.
For (1): At the first time. Now the board are running with null modem cable that is provided with the kit.
For (2): Yes, I am looking for the power good LED to flash?
Another question,
When... - MW 07:17 AM Software Development: RE: MityDSP-L138F Failure to Boot and Cannot Reset
- I am assuming these are out of the box Development kits?
For (1) the console UART, please ensure you are using the serial cable provided with the kit (I believe the board requires a null modem cable connection).
For (2), when you s... - CR 08:27 AM PCB Development: RE: Resistors in EMA signal and adress traces?
- Mike,
it's the L138-FX-225-RC Module. No FPGA.
I'm concerned about both kinds of traces.
Christian - MW 07:33 AM PCB Development: RE: Resistors in EMA signal and adress traces?
- Which part number? Specifically, does the module include an FPGA or not?
Which EMA traces are you concerned with, data lines, control, or both?
I do not believe there are any inline series resistors on the data or address lines.
... - Hi,
can anybody tell me if there are already resistors on the EMA-traces on the L138-Modul integrated? If yes, what are the values of them?
thanks,
Christian
04/02/2013
- Hello
I am using Industrial I/O board(80-000268RI-2 A) and 2 L138 board (L138-CG-225-RC ,L138-FG-225-RC).I got 2 issues:
(1) When I connect L138-CG-225-RC to Industrial I/O board. The Power Good LED lights up, and I can reset board, ...
03/28/2013
- Trying to install an intel 330 series SSD (60 Gb). I have a power brick for it and plugged that in. Connected to the SATA port (J503) and .... nothing. I saw the errata about Gen3 SATA drives, but there are no messages about atal or S...
03/26/2013
- MF 11:48 AM Software Development: RE: SPI NOR Flash memory map
- You are correct, Mike. The flash does have to be erased before writing. Here is a more fleshed out version of my code. It includes some checking for valid data before reading using a header, which others may not need but you get the id...
- MW 11:13 AM Software Development: RE: SPI NOR Flash memory map
- BTW:
It's not entirely clear to me if the write routine above will work properly. I don't know for sure, off-hand, if the driver is smart enough to do a FLASH erase prior to the write. And if it does, be aware that you will be erasi... - MW 11:11 AM Software Development: RE: SPI NOR Flash memory map
- The SPI partitions are defaulted in the board-mityomapl138.c file in arch/arm/mach-davinci in the spi_flash_partitions[] structure. This is where the kernel is getting these values.
If you want the partitions to show up right in MTD,... - FW 10:55 AM Software Development: RE: SPI NOR Flash memory map
- Please allow me to chime in with a similar question... I have "reorganized" the upper part of the spi nor flash on my mityDspL138 module as I have a Linux kernel that is larger than the original allocation. I have modified the uboot envi...
03/22/2013
- JT 03:13 PM Software Development: RE: Creating a Read-Only Filesystem
- I worked on it some more and ended up with a script with seven patch files that change it to a read-only filesystem. My plan is to setup a time delay relay that toggles the power to a board for a weekend test.
- MW 01:01 PM FPGA Development: RE: L138F - FPGA gets incorrect data from UPP
- Marek,
The UPP clocks may be sourced by either the FPGA or the OMAP-L138 based on your configuration requirements. If sourced by the OMAP-L138, you should be able to run the input clock to a DCM or a PLL and align the data-eyes on th... - Hello,
I have problem when trying to read data on UPP by FPGA (sent from OMAP - working with L138F, XC6SLX45, ISE WebPack 14.3). Data arrive corrupted. The reason might be latence on CLK when routed to clock tree via logic blocks in F...
03/20/2013
- JC 09:16 AM Software Development: RE: Creating a Read-Only Filesystem
- Jim,
Any luck? As far as I can tell that mount entry should work.
03/15/2013
- LM 11:32 AM Software Development: RE: MDK_2012-08-10 default configuration
- Mike,
Thanks for pointing that out - really helpful!
I can most definitely see the network (and boot from it) from U-Boot.
However, there is clearly some funny business going on with the PHY address;
U-Boot claims it finds the PHY a...
03/14/2013
- MW 08:25 PM Software Development: RE: MDK_2012-08-10 default configuration
- So the industrial IO board uses PHY address 3 and the EMAC driver is configured to look for that MDIO interface prior to initiating EMAC transfers. You will need to modify your kernel (make your own baseboard file or modify the industr...
- LM 07:06 PM Software Development: RE: MDK_2012-08-10 default configuration
- My custom board uses either PHY address 1 or 0 - both addresses cause the same problem.
I played around a little with the industrial base board and found that it does not suffer the same issue,
so there is most likely something in my ... - JT 08:59 AM Software Development: RE: Creating a Read-Only Filesystem
- I changed fstab for the /mnt/user_nand to as follows -
/dev/mtdblock1 /mnt/user_nand jffs2 defaults,rw,noatime,nodiratime 0 0
However, the power-up was the same and the partition was not mounted.
03/13/2013
- JC 04:06 PM Software Development: RE: Creating a Read-Only Filesystem
- > rm: cannot remove '/etc/volatile.cache': Read-only file system
> ...
Udev happens before the tmpfs entries get mounted from the fstab file. - JC 03:56 PM Software Development: RE: Creating a Read-Only Filesystem
- Your fstab entry doesn't have auto in the options list so it isn't auto mounted on startup. You should probably use the defaults and then override the options you want changed.
*defaults* Uses the default options that are rw, suid, d... - MF 01:20 PM Software Development: RE: SPI NOR Flash memory map
- This probably doesn't completely answer your question, but may be helpful. There is some "spare" memory on the SPI NOR flash.
On your target try: - MW 10:59 AM Software Development: RE: MDK_2012-08-10 default configuration
- What PHY address does your custom baseboard use?
-Mike
- Hi,
I am working on bringing up a custom base board for a MityDSP-L138.
Most things seem to work fine using the version of Linux installed on the MityDsp-L138 board out of the box. However, I need to reconfigure the kernel a bit to re...
03/12/2013
- LA 02:59 PM Software Development: RE: FPGA Memory Size
- You are correct we are looking at cs5 as well.
32k would probably be sufficient. We typically prefer to provide the information in a flat manner to offload the CPU from parsing, or having to copy out all the information instead of the... - JT 01:52 PM Software Development: RE: Creating a Read-Only Filesystem
- I had used -
mount -t jffs2 /dev/mtdblock1 /mnt/user_nand
and just -
mount /mnt/user_nand
also works.
- JC 01:42 PM Software Development: RE: Creating a Read-Only Filesystem
- "I can manually mount /mnt/user_nand and access that partition"
Whats the full command you use to manually mount your partition? Does @mount /mnt/user_nand@ work? - Hi,
We use the MityDSP-L138 in a factory automation product and need to prevent fs corruption from random shutdowns. My first attempt was to change the rootfs to read-only in a startup script, but it would be safer if the rootfs was rea... - JC 08:32 AM Software Development: RE: SPI NOR Flash memory map
- This appears to be what your looking for.
[[MityDSP-L138_Architecture]]
Also can be determined by looking at the uboot environment variables. The erase commands give the starting address and the max size expected for each image.
@
... - (posted for a customer)
We are looking at using the SPI flash and/or NOR flash for storing our software on the L138 SOM. We are currently using uBoot and the exisiting boot code on the board so we do not want to overwrite these.
...
03/11/2013
- MW 07:58 PM Software Development: RE: FPGA Memory Size
- As mentioned on the "EMIFA wiki page":http://support.criticallink.com/redmine/projects/arm9-platforms/wiki/EMIF_Interface, all of our FPGA fabric and drivers use CE5 space (0x66000000), for the ARM or the DSP (where did you find informat...
- The standard FPGA memory available to the arm processor within angstrom is currently limited to 2k.
From what we can gather there are many places that could work together to create this limit:
Flash code
uBoot
FPGA vhdl
Linux dr... - MC 12:49 PM FPGA Development: RE: SPI Core on FPGA: Implementation on MityDSP-L138F
- Dear all,
I'm trying to understand the behaviour of your SPI core on FPGA with hooked FIFO and wondering how to connect it to a PulSAR ADC (for example AD7980) from Analog Devices, hopefully, on SW side, using your tcDspFpgaSpi Class in...