Activity
From 12/07/2011 to 01/05/2012
12/09/2011
- ME 08:57 AM Software Development: RE: Using the EMIFA interface on the Mitydsp-1810
- We changed chip select to CS4 and kept having the same issues. We've done some other measurements and tests and we now doubt it's some kind of contention, it is most likely some problem on the ASIC side rather than the arm side of things...
- MW 07:39 AM Software Development: RE: Using the EMIFA interface on the Mitydsp-1810
- Hi Mattias,
The only chip select used on the EMIFA by default is CS3 (used for the NAND). Our FPGA driver framework uses CS5, but if you don't load the modules for the drivers (e.g., fpga_ctrl.ko) then that CS should not be used duri... - ME 03:58 AM Software Development: RE: Using the EMIFA interface on the Mitydsp-1810
- Hi,
I was wondering which chip selects are unused by default? What I can see in the u-boot and linux source is that only CS2 and CS3 are used. We're using chip select 5 right now but we're having some issues and I'm not sure what's ca...
12/07/2011
- SW 04:37 PM FPGA Development: RE: FPGA load causes reboot
- Mike,
Your .bin file loaded up fine. I had the designer look at the build, and he had some IO not constrained corectly. I think it might have been to the EMIFA interface. He has fixed that and I was able to load up the build and acce... - MW 09:38 AM FPGA Development: RE: FPGA load causes reboot
- Scott,
My suspicion is that the pins tied to the EMIFA (a chip select line, a wait line, or perhaps the data lines) are being driving when they shouldn't be. I would double check your bitstream configuration options for unused IOBs, ...