Activity
From 07/07/2011 to 08/05/2011
08/05/2011
- I have the mitydspl138, baseboard, and the standard Critical Link Linux kernel. When I plug a usb flash drive into the type A slot, I get a log message:
usb 1-1: new full speed USB device using ohci and address 18
However, it does ...
08/03/2011
- MW 10:17 AM FPGA Development: RE: Programming the FPGA
- The pwm.ngc should be included in the 2011-08-01 MDK release (just published).
-Mike
- CM 09:41 AM FPGA Development: RE: Programming the FPGA
- I successfully built this project but I had to comment out anything related to pwm. Seems I do not have the pwm.ngc netlist file. Also generated the correct .bin file same as what you guys provided.
07/29/2011
- CM 11:37 AM FPGA Development: RE: Programming the FPGA
- Thanks Mike. I picked up the common VHDL files with no trouble.
However, when I tried to add a netlist file (.ngc?), I got an error that indicates a different FPGA than I have (for which the project was built).
How can I get the co... - MW 07:30 AM FPGA Development: RE: Programming the FPGA
- Hi Craig,
Yeah, the Xilinx ISE file format really doesn't use relative path names very well.
As far as the VHDL, all of the common/base VHDL needed to build the top level (EMIF interface, the base module, the core_version module, e...
07/27/2011
- MW 05:28 PM Software Development: RE: NAND controller, EDMA3 and EMIFA priorities
- Hi Mads,
I'm not sure there is much more you can do than what is already configured.
You might consider cross posting this over on "TI's E2E site":http://e2e.ti.com/?DCMP=E2E_E2E_E2E&CMP=KNC-GoogleTI&247SEM, as this is sort of a ge... - Hi
I have a few questions regarding the NAND flash and EMIFA.
From the EDMA priority settings below (which I just dumped directly from the registers)
MSTPRI0 = 0x44442222
MSTPRI1 = 0x44440000
MSTPRI2 = 0x54604404
It seems EDM... - MC 05:05 PM Software Development: RE: Mapping code to IRAM
- Hi Mark
You could try the #pragma CODE_SECTION(<function name>, "mysect") (In C++ you omit the function name and places the pragma before the declaration). You will probably have to define your own section in the CMD file.
Look at ...
07/26/2011
- TC 05:14 PM Software Development: RE: Mapping code to IRAM
- Hi Marc -
I'm not sure we will have the answer to this question as it's really a TI question. While we're waiting for a response from my team you may also wish to post it on the TI e2e forums.
Tom - Hey All,
I am using CCS4 and SYS/BIOS to program the DSP core in the L138, and I am trying to figure out how to specify the linker option so that a certain C function gets mapped into IRAM, instead of DDR. When I look at the C/C++ Bui... - CM 09:43 AM FPGA Development: RE: Programming the FPGA
- I opened this project file in XISE and it yelled at me for a number of VHD files (see attached png).
example.zip - XISE project and source for IndustrialIO.bin - LX45 Industrial IO Board FPGA (no display support) (60.1 KB)
Is this ...
07/24/2011
- CM 08:44 PM FPGA Development: RE: Programming the FPGA
- Success has been achieved. Thanks Mike!
I loaded the stock uImage from the .run file supplied with the kit. That did the trick - I can now startup the board, it flushes and then automatically loads the FPGA during boot all the way to ... - MW 12:55 PM FPGA Development: RE: Programming the FPGA
- Hi Craig,
I think you need to modify the bootargs assuming the NAND has a valid filesystem on it.
See "this wiki page":http://support.criticallink.com/redmine/projects/arm9-platforms/wiki/Linux_Root_File_System.
Specifically, yo... - CM 09:45 AM FPGA Development: RE: Programming the FPGA
- The uImage_Indio_20110723 kernel image booted but could not mount to a filesystem.
Getting closer!
I attached the full bootlog.
07/23/2011
- CM 12:52 PM FPGA Development: RE: Programming the FPGA
- Thanks Mike.
My plan is to also extract the image from the .run file and try both this afternoon.
I am using the Industrial I/O baseboard.
I would also be interested in building an image from source. As you indicated yesterday t... - MW 11:40 AM FPGA Development: RE: Programming the FPGA
- Hi Craig,
I am attaching a uImage file built for the Industrial I/O board from our kernel code baseline.
This really should work for your set up, assuming you are using an Industrial I/O baseboard.
Your steps should also get you... - CM 10:57 AM FPGA Development: RE: Programming the FPGA
- Hey Mike,
Late yesterday I booted into UBOOT; cleared the bootfpga (setenv bootfpga;saveenv); rebooted with Angstrom image and still got stuck at "Starting kernel..."
I tried twice just to make sure I did NOT get FPGA DONE LED.
... - MW 09:04 AM FPGA Development: RE: Programming the FPGA
- Hi Craig,
Just following up. Are you still DOA? Or did not programming the FPGA clear the issue?
-Mike
07/22/2011
- CM 01:24 PM FPGA Development: RE: Programming the FPGA
- Good point. I'll defer any FPGA programming until I resolve the linux kernel load.
Here's the boot text. You can see the auto FPGA programming in the text. I'll turn that off and try again,
OMAP-L138/AM-1808/AM-1810 initialization ... - MW 01:14 PM FPGA Development: RE: Programming the FPGA
- Also,
Can you dump the entire boot text from power up to hang? Would like to see all the commands executed by the bootloader.
-Mike
- MW 01:13 PM FPGA Development: RE: Programming the FPGA
- Hi Craig,
Are you programming the FPGA before you load the kernel? The FPGA can cause problems with the kernel load if you are driving unused pins that might be tied to interrupt lines or NMI lines.
You may need to build that late... - CM 01:06 PM FPGA Development: RE: Programming the FPGA
- I tried again in case I screwed up the first time.
I also tried the uImage file in /boot on another of our boards. That image got stuck in the same way.
From files area: Linux-2.6.34-rc1-07430-g2e70fb6
From another of our dev kits...
07/21/2011
- CM 05:00 PM FPGA Development: RE: Programming the FPGA
- Hi Greg,
Thanks for XISE files.
I followed instructions from Linux Kernel installtion using uImage from files area and the boot gets stuck as shown below (starting kernel). Maybe I need the uImage file that came preloaded on the bo... - GG 02:03 PM FPGA Development: RE: Programming the FPGA
- Hi Craig,
I've attached the project file used to build the .bin file I posted earlier. You'll need to link against our cores in order to build this project, and those can be found in the latest MDK release.
\Greg - CM 02:02 PM FPGA Development: RE: Programming the FPGA
- The revised read instruction works!
We have the L138-FI-225-RC. My mistake. I was looking at the wrong line in the orderable section in the L138 SOM spec.
Thanks for all your support in our "startup" activities. In me you are deali... - MW 01:43 PM FPGA Development: RE: Programming the FPGA
- Hi Craig,
For the bootgpga image, you need to read out all of the image into RAM before trying to program the FPGA.
I think you need to change: - CM 01:03 PM FPGA Development: RE: Programming the FPGA
- Question on automatically loading the FPGA at boot...
I've followed these instructions:
loadb 0xC0700000
[send the correct IndustrialIO.bin using kermit]
sf probe 0
sf erase 0x580000 0x170000
sf write 0xC0700000 0x580000 ${fi... - CM 12:21 PM FPGA Development: RE: Programming the FPGA
- Can you guys zip up and post or e-mail me source files used to generate this .bin?
I would like to play some with the FPGA.
IndustrialIO.bin - LX45 Industrial IO Board FPGA (no display support) (1.4 MB) - CM 11:09 AM FPGA Development: RE: Programming the FPGA
- Hi Tim.
I'm on my 3rd USB-to-serial adapter and 4th attempt at driver update. I'm sure some manager got a nice bonus for taking cost out of these adaptors.
I've finally programmed the flash. The board now boots to U-BOOT with no pr... - CM 10:15 AM FPGA Development: RE: Programming the FPGA
- Hi Tim,
Do I need a different version of SPIWriter_MityDSP-L138.out? Didn't see this file in the latest zip.
I tried this latest version of the utility with these results. A little different - also read error prior to BOOTME receiv... - TI 09:07 AM FPGA Development: RE: Programming the FPGA
- Craig
I have uploaded the latest serial programming utility to the files section.
Try that and see if it corrects your timeout issue.
cheers
/Tim - CM 08:22 AM FPGA Development: RE: Programming the FPGA
- I've tried several other usb to serial adaptors with no luck.
I get the same error:
(AIS Parse): Performing Opcode Sync...
(Serial Port): Read error! (The operation has timed out.)
(AIS Parse): I/O Error in read!
Do I have the ...
07/20/2011
- CM 12:10 PM FPGA Development: RE: Programming the FPGA
- Yes. I'm using USB to serial dongle. It's unbranded using Prolific chipset. Unfortunately I do not have a "real" serial port on my laptop.
I've tried this several times with same result.
Full version on sfh_OMAP-L138.exe is 1.67.38... - TI 10:43 AM FPGA Development: RE: Programming the FPGA
- Craig
I see your serial port is COM7.. I presume that is a USB serial dongle? What brand / model is it? We have had some troubles with various dongles trying to push lots of data across them. Can you run it using a "real" serial port?
... - CM 10:25 AM FPGA Development: RE: Programming the FPGA
- Tried dead board instructions (sfh_OMAP-L138 -flash -v -p COM7 UBL_SPI_MEM.ais u-boot.bin) and I get read error:
(AIS Parse): Read magic word 0x41504954.
(AIS Parse): Waiting for BOOTME... (power on or reset target now)
(AIS Parse):... - TI 09:01 AM FPGA Development: RE: Programming the FPGA
- Craig
If you set the bootfpga environment var, uboot will automatically run the commands at startup. I'm not exactly sure when in the boot process it runs, but it is fairly early one.
cheers
/Tim
p.s. Don't forget to run the saveen... - CM 08:57 AM FPGA Development: RE: Programming the FPGA
- Good news / bad news.
It was a successful load. Green DONE led lit.
However, I apparently hammered the flash with an incorrect sf statement. I'm going to follow the dead board instructions to unbrick this board.
In the meantime,...
07/19/2011
- GG 05:06 PM FPGA Development: RE: Programming the FPGA
- Hi Craig,
I've attached a .bin file that should work for you (in the future we will add LX45 example .bin files to the MDK releases).
As far as the bootfpga command, the following should work for the LX45: - CM 02:49 PM FPGA Development: RE: Programming the FPGA
- Hi Greg.
This command worked: U-Boot > sf erase 0x580000 0x170000
But you are right. I still have issues.
I got the IndustrialIO.bin file from the Wiki: [[http://support.criticallink.com/redmine/projects/arm9-platforms/wiki/Prog... - GG 01:50 PM FPGA Development: RE: Programming the FPGA
- Hi Craig,
The flash erase needs to be page aligned. This should work: - CM 01:22 PM FPGA Development: RE: Programming the FPGA
- Tim - I think we are getting close.
Here's the result:
U-Boot > sf erase 0x580000 0x16b000
SPI flash erase failed - TI 12:53 PM FPGA Development: RE: Programming the FPGA
- Craig
Aha!
The default size for uboot's loadfpga command (and what is shown on the wiki!) is 0x80000 (1/2MB), which is for the LX16 part.
For the LX45 part, the file is much larger (1484404 bytes [ 0x16A674]), so all the parameters w... - CM 11:49 AM FPGA Development: RE: Programming the FPGA
- Thanks Tim.
No DONE led yet but looks as if I made progress:
U-Boot > sf probe 0; sf read 0xc0700000 0x580000 0x80000; loadfpga 0xc0700000
8192 KiB M25P64 at 0:0 is now current device
Loading FPGA from 0xC0700000 with 0x80000 by... - TI 11:43 AM FPGA Development: RE: Programming the FPGA
- Craig,
another thing to check is that the configuration of the device is correct.
if you run factoryconfig at the U-Boot> prompt it will tell you what the FPGA and Part Numbers are.
Make sure that this info jives with what you really ... - TI 11:32 AM FPGA Development: RE: Programming the FPGA
- Craig
The DONE led should go on immediately after programming the FPGA.
Can you try running the commands in the bootfpga variable from the prompt?
ie:
uBoot> sf probe 0; sf read 0xc0700000 0x580000 0x80000; loadfpga 0xc0700000
and s... - I'm following these Wiki instructions and I'm not getting the DONE led:
U-Boot > loadb 0xC0700000
## Ready for binary (kermit) download to 0xC0700000 at 115200 bps...
## Total Size = 0x00071544 = 464196 Bytes
## Start Addr = 0xC070...
07/15/2011
- MW 11:18 AM Software Development: RE: MityDSPl138 JTAG
- Marc,
Try stopping the ARM in the u-Boot phase and see if you can connect to the DSP then. The linux portion of ARM holds the DSP in reset by default, and it may be that the emulator can't break into the DSP with the emulator when it... - Hey All,
I have the XDS100V1 JTAG emulator, and I'm trying to connect to the DSP core with CCS4, but it does not seem to be working. Are there any steps that have to be taken to get the board working with the JTAG connection (other t... - MC 07:17 AM Software Development: RE: MITYDSP OMAP-L138 EMIF FPGA / NAND shared bus access
- Hi Mike
I have a few questions regarding the NAND flash and EMIFA.
As you earlier mentioned I could try adjusting the EDMA priority settings.
From the EDMA priority settings below (which I just dumped directly from the registers) ...
07/14/2011
- MW 02:03 PM Software Development: RE: uPP/DMA registers
- You will definitely need to configure the pin mux. You should assume that the UPP is powered down (in the reset state) as well. You may need to add the UPP clock to the clock tree in linux and turn it on, I haven't checked if that has ...
- SW 01:58 PM Software Development: RE: uPP/DMA registers
- Mike,
Thanks for the link to the OMAP specification. I think that is all I needed to start work on my driver. In the default mityDSP configuration, are the clocks and power enabled to the uPP? I assume I will need to set the pin m... - MW 01:13 PM Software Development: RE: uPP/DMA registers
- Hi Scott,
Unfortunately, TI (nor Critical Link) provides linux drivers for the UPP.
The memory map that includes the base address of the UPP peripheral is in the "OMAP-L138 specification":http://www.ti.com/lit/gpn/omap-l138. The r... - Hello,
I want to use the uPP and EMIFA to pass data between an FPGA and the ARM on the OMAP. I think I've got what I need for the EMIFA, pick one of the available chip selects and create a driver to remap that memory. I'm a bit lost...
07/13/2011
- MW 03:17 PM Software Development: RE: Default Clock Speed
- No, it won't change the clocks. It will just feed the RTOS the correct numbers.
You really should set the frequency using the ARM unless you are not running any OS on it at all. The linux OS needs to know about changes made to the P... - ML 02:55 PM Software Development: RE: Default Clock Speed
- Will GBL_setFrequency(); actually change the clock, or just feed the RTOS will correct numbers like you were talking about?
My goal is to set the OMAP to 375MHz, preferably using the DSP and CCS. - MW 02:49 PM Software Development: RE: Default Clock Speed
- Hi,
I want to clarify a couple of things here.
The DSP and the ARM clocks are driven by the same system clock. Modifying the ARM modifies the DSP clock.
The MityDSP modules (i.e., the OMAP-L138/ARM-1808/ARM-1810) come up at 300... - GG 02:07 PM Software Development: RE: Default Clock Speed
- Hi Marc,
The boards default to running at 300 MHz, though they can be run at 456 MHz. You can change this in the DSP in two ways. You can do this statically by double clicking the .tcf file in your project, going to "Global Settings,"... - Hey All,
What speed will an out of the box MityDSP-L138 run at? I was under the assumption it was 456MHz, but when I look in the provided .tcf it says 300MHz. Any information would be much appreciated.
-Marc